Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Instruction Set Architecture Block Transition Lookaside Buffer (BTLB)
� Software: If software TLB miss handling is implemented, a TLB miss fault interruption routine
performs the translation. It inserts the translation and protection fields in the TLB and afterward
restarts the interrupted routine, in which the TLB miss occurred.
2.3.4 Block Transition Lookaside Buffer (BTLB)
Similar as the TLB, the BTLB provides virtual-to-physical address translations. However the BTLB
maps large address ranges rather that single pages as the TLB does. These large address ranges are
called block translations and therefore stored in the Block Translation Lookaside Buffer. These block
translations are useful for virtual address ranges that do not get paged in or out.
BTLBs were only implemented on 32-bit PA-RISC processors (PA-7x00), the 64-bit versions instead
implement variable page sizes, thus any entry can be of >4k mapping.
2.3.5 Superscalar execution
Overview
A superscalar processor implementation decodes, dispatches and executes multiple instructions per
cycle if dependencies between the instructions permit. This is possible if the instruction stream contains
independent instructions. Superscalarity can be easily gained from an decoupled floating point unit
(FPU) which executes floating point operations (calculations) indepently from the (integer) ALU. More
complicated variations allow for parallel load/store operations, integer calculations et al, which need a
more complex CPU design that analyzes the instructions/branches.
Every PA-RISC processor from the PA-7100 upwards implements superscalar execution. Instructions
proceed together through the execution pipeline which is called instruction bundling. The superscalar
execution is functionally transparent to the software, the effects of any given instruction are the same
whether it was executed as part of a bundle or alone. Bundling rules are applied at run-time by the
hardware; optimal performance may only be gained by proper ordering of the instructions so the
processor can use its full superscalar potential.
Several kinds of restrictions are placed upon the instruction bundling:
� Functional unit contention
� Data dependency restrictions
� Control flow restrictions
� Special instruction restrictions
For bundling purposes, all instruction are divided into classes:
Table 2.3: PA-RISC superscalar instruction classes
Class Description
FLOP Floating point operation
LDST Loads and stores
ALU Integer ALU
MM Shifts, extracts, deposits
NUL Might nullify successor
BV Branch Vectored (BV) local, Branch (BE) external
BR Other branches
FSYS FTEST and FP status/exception
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