Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC System Architecture
2.4 PA-RISC System Architecture
2.4.1 32-bit systems
Early designs
Early 32-bit systems (1980s TS-1, NS-1, NS-2 and PCX) use custom designs, with most based on the
SIU/SPI main bus interfaces attaching the CPU to the SMB bus. In most cases the system processing
and I/O units are made up of a large number of individual chips forming the central chipset and using
the CIO and HP-PB I/O buses.
1. System controllers (SIU or SPI) attach the CPU with its execution units to the SMB system main
bus
2. System Main Bus (SMB) is the central bus, to which CPU, memory and I/O buses attach
� CPU attaches via SIU/SPU to SMB with 64-bit at 25-30 MHz
� Memory attaches to SMB
� Some: Memory extensions attach to SMB (via MABs; see below)
3. Central Bus/Midbus (CTB) attaches the I/O via bus convertes to SMB
� Attaches via 32-bit at maximum of 10 MHz at SMB
� Two CTBs per SMB
4. CIO buses, up to three, attach via adapters to CTB
� Attaches via 16-bit at 4 MHz (probably dependant on CTB clock)
� I/O expansion cards plug into CIO slots
5. Some systems only: Memory Array Buses (MABs) attach to SMB for more memory
ASP/Viper
� Attaches via 64-bit (with ECC 72-bit) at SMB
PA-7000 and PA-7100 systems use the ASP chipset and Viper memory controller. They utilize the VSC
CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using HP-PB I/O
buses, all provided by separate I/O adapters/bus bridges.
1. PBus is the main processor and memory bus
� CPU attaches to PBus with 32-bit (with ECC 40-bit)
2. Viper, the main memory and I/O controller attaches to PBus
� Memory attaches to MIOC via 64-bit (with ECC 72-bit)
3. VSC, the system main bus, attaches to MIOC and various I/O controllers
� Attaches via 32-bit (PA-7000) or 64-bit (PA-7100) at MIOC
4. I/O adapters attach to VSC
� Either ASP chipset for SGC or GSC bus systems, or HP-PB adapters for some servers
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