Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Processors PA-7200 (PCX-T’)
2.2.7 PA-7200 (PCX-T’)
Overview
The PA-7200 completely revised the PA-7100 processor core, leveraging only the FPU in its release in
early 1995. Being a two-way superscalar processor, the PA-7200 can dispatch and execute two separate
instructions at a time to its functional units. In contrast to the PA-7100 it has two separate integer ALUs
and thus can execute two ALU integer operations simultaneously. Other changes include a redesigned
cache architecture — while retaining the general cache layout with large off-chip L1 caches at CPU
clock speed — and use of the Runway processor bus, carried on to later PA-8x00 processors. The
PA-7200 was targeted towards high-performance general-purpose applications, but also on specialized
applications with large working sets which could take advantage of the high-bandwidth bus interface.
Details
� PA-RISC version 1.1d 32-bit
� Three functional units: 2 integer ALUs, 1 Floating Point
� 2-way superscalar
� SMP-capable
� FPU, MMU, cache controller integrated on die, memory and I/O controller separate and off-chip
� Five-stage pipeline
� 2 KB on-chip “assist” L1 cache, fully associative, holds 64 32-Byte cache lines
� Off-chip L1 caches up to 1 MB I and 2 MB D realized in asynchronous SRAMs with one cycle
latency
� (The 2 KB on-chip assist cache is not really considered a true cache, thus the off-chip cache is the
system’s L1 cache.)
� Caches are 64-bit per access, direct mapped, parity protected and cycled at CPU speed
� Caches are virtually indexed and physically tagged to minimize latency
� 120-entry fully associative TLB
� 16-entry BTLB
� Hardware TLB miss support
� Six predecode bits
� Support for uncached memory pages
� Bi-endian support
� Runway system interface, 64-bit wide, 120 MHz, 960 MB/s peak bandwidth, CPU-to-bus frequency
ratios of 1.0, 0.75 and .67 processor speed possible
� Glueless interface to the Runway system bus for up to four-way SMP (four CPUs on same Runway
processor bus)
� Can have up to six bus-transactions in progress at once
� CPU interfaces to U2 I/O adapters and MMC/SMC memory controllers on the Runway bus
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