Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC System Architecture 64-bit systems
Multiprocessor attachment
LASI
1. Two-way SMP ( “Low Cost” ): Two CPUs share a PBus and attach to the same MIOC. Memory
attaches directly to MIOC, I/O attaches via VSC to MIOC.
2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which
I/O and memory attach.
PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines most
functions and I/O on a single chip, and an on-CPU MIOC memory controller. These system use GSC
or GSC+ as main bus and a variety of expansion buses via bus adapters, ranging from HSC/GSC, EISA
to PCI and VME. EISA is provided by Wax, PCI by Dino.
On the two 32-bit LC “Low Cost” processors PA-7100LC and PA-7300LC GSC is the main system bus.
The CPUs integrate the external memory and I/O controller (MIOC) onto the processor (mostly used
with LASI chipsets), with memory and cache directly attaching to it.
1. MIOC, main memory and I/O controller, directly integrated on the CPU
� Execution units and internal caches attach on-chip to the MIOC
� External cache and memory attach to MIOC
2. GSC, system main bus, attaches to MIOC and I/O controllers
� Attaches via 32-bit
� PA-7300LC systems use extended GSC+
3. I/O adapters attach to GSC
References
� LASI chipset
� Some video adapters directly attach to GSC
� I/O slots extend GSC
� Bus adapters, including EISA, VME and PCI, attach to GSC (includes WAX — a modified
LASI — , Dino, and custom chips)
1. An I/O System on a Chip 58 Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)
2.4.2 64-bit systems
U2/Uturn Runway
The 64-bit PA-8000 and some PA-8200 systems use U2/Uturn I/O adapters, which attach two GSC/HSC
buses to the main Runway bus, and MMC/SMC memory controllers. I/O is realized on the GSC bus
with the LASI chipset and Wax and Dino I/O adapters.
58 http://www.hpl.hp.com/hpjournal/95apr/apr95a4.pdf
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