Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Chipsets MMC/SMC
� Up to four DEWs were implemented in actual single systems for up to eight processors
Used in
� L1500 (rp5430), L3000 (rp5470)
� N4000 (rp7400)
References
� See Stretch chipset references
2.5.16 MMC/SMC
Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and
SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is
controlled by the U2/UTurn I/O adapters on the same Runway bus.
Details
� Master Memory Controller (MMC) is the main memory controller and attaches with 64-bit to
the Runway processor bus and 128-bit to the memory data bus (via the DMs)
� Slave Memory Controllers (SMCs) are the secondary memory controllers and attach to the MMC
main memory controllers. Up to eight SMCs attach to one MMC on its memory address bus. The
SMCs carry the functionality to interface with specific types of DRAM.
� Data Multiplexers (DMs) attach the 128-bit 60 MHz data bus of the MMC to the four sets of
memory. Each two sets of memory connect with two 64-bit 30 MHz buses to the DMs. The DMs
are not used in all systems.
� Memory data bus from MMC to DMs/memory 128-bit wide, with 60 MHz peak bandwidth
(960 MB/s data rate)
� Physical address space of 36-bit (32 GB main memory)
� Memory address bus is shared between all SMCs of a MMC, 39-bit at 60 MHz
� Memory data bus attaches to the DMs and memory
� Memory attaches to their private SMCs for addresses and to Data MUXes for data
� Up to 32-way memory interleaving (four-way per SMC)
� MMC is a 432-pin PGA chip
� SMCs are 208-pin MQUAD chips
� DMs are 160-pin POFP chips
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