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Chapter 4 PA-RISC Computer Systems - OpenPA.net

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<strong>PA</strong>-<strong>RISC</strong> Chipsets Memory and I/O Controller (MIOC)<br />

References<br />

1. Midrange <strong>PA</strong>-<strong>RISC</strong> Workstations with Price/Performance Leadership 76 (.pdf) pp. 6-11 Andrew<br />

J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)<br />

2. VLSI Circuits for Low-End and Midrange <strong>PA</strong>-<strong>RISC</strong> <strong>Computer</strong>s 77 (.pdf) pp. 12-22 Craig A. Gleason<br />

(August 1992: Hewlett-Packard Journal)<br />

3. High-Performance Design for Low-Cost <strong>PA</strong>-<strong>RISC</strong> Desktops 78 (.pdf) pp. 56-63 Craig Fink et al<br />

(August 1992: Hewlett-Packard Journal)<br />

2.5.14 Memory and I/O Controller (MIOC)<br />

The Memory and I/O Controller in the <strong>PA</strong>-7100LC and <strong>PA</strong>-7300LC processor integrates DRAM/cache<br />

and I/O controller onto the processor die. It is similar on both CPUs, with the <strong>PA</strong>-7300LC MIOC<br />

having wider data paths to L2 cache and RAM and supporting the advanced GSC+ bus over the older<br />

GSC.<br />

The integrated memory controller requires only buffers and DRAM modules to build up the complete<br />

memory subsystem. The <strong>PA</strong>-7300LC memory controller includes a Second Level Cache Controller<br />

(SLC), which provides an optional L2 cache, ranging from 32 KB to 8 MB. It shares the data bus with<br />

the DRAM subsystem, so it has the same width (64/128-bit) and same optional SEDC error control.<br />

Details<br />

� Execution units and internal caches attach on-chip to the MIOC<br />

� External cache (L1 on <strong>PA</strong>-7100LC, L2 on <strong>PA</strong>-7300LC) attach to MIOC via 64-bit (<strong>PA</strong>-7100LC)<br />

or 128-bit (<strong>PA</strong>-7300LC), both with ECC<br />

� Memory attaches to MIOC via 64-bit (on <strong>PA</strong>-7100LC) or 128-bit (<strong>PA</strong>-7300LC), with ECC<br />

� On <strong>PA</strong>-7300LC memory lines use the L2 cache data lines<br />

� GSC, the system main bus attaches to MIOC<br />

� On <strong>PA</strong>-7300, GSC+ system main bus<br />

� Support for 4, 16, 64 and 256 Mbit modules<br />

� Support for both FPM and EDO DRAM<br />

� Optional SEDC error control<br />

� Up to 16 physical memory slots<br />

� Support for a wide range of core frequencies<br />

� Support for 3.3 V and 5.0 V DRAM<br />

76 http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1992-08.pdf<br />

77 http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1992-08.pdf<br />

78 http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1992-08.pdf<br />

67

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