Chapter 4 PA-RISC Computer Systems - OpenPA.net

Convex Exemplar SPP1000, SPP1200 & SPP1600 Internals
� SPP1000/XA Cluster: 8-128 PA-7100 100 MHz with 1/1 MB off-chip I/D L1 cache each
� SPP1200/CD: 2-16 PA-7200 120 MHz with 256/256 KB off-chip I/D L1 cache each
� SPP1200/XA Hypernode: 2-8 PA-7200 120 MHz with 256/256 KB off-chip I/D L1 cache each
� SPP1200/XA Cluster: 8-128 PA-7200 120 MHz with 256/256 KB off-chip I/D L1 cache each
� SPP1600/CD: 2-16 PA-7200 120 MHz with 1/1 MB off-chip I/D L1 cache each
� SPP1600/XA HyperNode: 2-16 PA-7200 120 MHz with 1/1 MB off-chip I/D L1 cache each
� SPP1600/XA Cluster: 8-128 PA-7200 120 MHz with 1/1 MB off-chip I/D L1 cache each
It is not quite clear how the CD models relate to the XA models — the XA clusters consist of several 2-8
processor hypernodes while the CD models were shipped with up to 16 processors. Either the CDs are
different machines than the XA hypernodes or they are simply two XA hypernodes coupled together,
without any additional SCI/CTI expansion possibilities.
Chipset
The chipset is based completely on an own Convex design and centers around the Convex five-port
crossbar, later improved on the SPP2000 with eight ports and used in HP’s V-Class.
1. 5x5 nonblocking crossbar, with five crossbar ports, is the central part of the system, it connects
to four “functional units” (memory, SCI links and processor) and with the fifth port to the local
system I/O. The four functional units contain each a memory controller, SCI controller and
an “agent” for two processors. Memory and processor use different data links to the crossbar
— memory access always goes over the crossbar, even from a processor to the memory in the
same functional unit. Each crossbar port has a data rate of 250 MB/s, giving the crossbar a combined
peak bandwidth of 1.25 GB/s. The crossbar is implemented in Gallium arsenide gate arrays
(GaAs, 250K transistors), quite a rarity, since it was very expensive and difficult to handle.
2. Four CPU Agents attach to the crossbar and provide access for the processors to the memory via
the crossbar over a 250 MB/s crossbar port shared with the memory controller (see below).
3. Four Convex Coherent Memory Controllers (CCMCs) attach each one four-way interleaved
memory board to the crossbar. The CCMCs additionally do cache coherency and interface to
the Convex’s SCI (CTI) link for inter-hypernode connection. [It is not quite clear if the CCMCs
share the whole 250 MB/s port/data connections with the CPU agents on the same functional unit,
or if CCMC and CPU agent attach to separate lines of the crossbar port — Ed.] The CTI interface
— or the complete CCMC — were apparently also GaA chips.
4. Exemplar I/O (Input/Ouput) Subsystem connects to the fifth 250 MB/s crossbar port and attaches
the I/O subsystem controllers to the crossbar and this memory and processors.
Buses
� Total crossbar bandwidth 1.25 GB/s (five 250 MB/s ports)
� CPU/Memory bandwidth 1.0 GB/s (four 250 MB/s ports shared with memory)
� I/O bandwidth 250 MB/s (one crossbar port)
� SPP1000: Four SBus I/O buses for expansion slots
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