ARM Compiler toolchain Using the Linker - ARM Information Center

5.14 Factors that influence function inlining
5.14.1 See also
The following factors influence the way functions are inlined:
Using linker optimizations
• The linker handles only the simplest cases and does not inline any instructions that read
or write to the PC because this depends on the location of the function.
• If your image contains both ARM and Thumb code, functions that are called from the
opposite state must be built for interworking. The linker can inline functions containing
up to two 16-bit Thumb instructions. However, an ARM calling function can only inline
functions containing a single 16-bit Thumb instruction or 32-bit Thumb-2 instruction.
• The action that the linker takes depends on the size of the function being called. The
following table shows the state of both the calling function and the function being called:
Calling function
state
Called function
state
The linker can inline in different states if there is an equivalent instruction available. For
example, if a Thumb instruction is adds r0, r0 then the linker can inline the equivalent
ARM instruction. It is not possible to inline from ARM to Thumb because there is less
chance of Thumb equivalent to an ARM instruction.
• For a function to be inlined, the last instruction of the function must be either:
MOV pc, lr
or
BX lr
A function that consists only of a return sequence can be inlined as a NOP.
• A conditional ARM instruction can only be inlined if either:
— The condition on the BL matches the condition on the instruction being inlined. For
example, BLEQ can only inline an instruction with a matching condition like ADDEQ.
— The BL instruction or the instruction to be inlined is unconditional. An unconditional
ARM BL can inline any conditional or unconditional instruction that satisfies all the
other criteria. An instruction that cannot be conditionally executed cannot be inlined
if the BL instruction is conditional.
• A BL that is the last instruction of a Thumb-2 If-Then (IT) block cannot inline a 16-bit
Thumb instruction or a 32-bit MRS, MSR, or CPS instruction. This is because the IT block
changes the behavior of the instructions within its scope so inlining the instruction
changes the behavior of the program.
Concepts
• Handling branches that optimize to a NOP on page 5-21.
Using the Assembler:
• Conditional instructions on page 6-2.
Table 5-1 Inlining small functions
ARM ARM 4 to 8 bytes
ARM Thumb 2 to 6 bytes
Called function size
Thumb Thumb 2 to 6 bytes
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