ARM Compiler toolchain Using the Linker - ARM Information Center

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5.14 Factors that influence function inlining 5.14.1 See also The following factors influence the way functions are inlined: Using linker optimizations • The linker handles only the simplest cases and does not inline any instructions that read or write to the PC because this depends on the location of the function. • If your image contains both ARM and Thumb code, functions that are called from the opposite state must be built for interworking. The linker can inline functions containing up to two 16-bit Thumb instructions. However, an ARM calling function can only inline functions containing a single 16-bit Thumb instruction or 32-bit Thumb-2 instruction. • The action that the linker takes depends on the size of the function being called. The following table shows the state of both the calling function and the function being called: Calling function state Called function state The linker can inline in different states if there is an equivalent instruction available. For example, if a Thumb instruction is adds r0, r0 then the linker can inline the equivalent ARM instruction. It is not possible to inline from ARM to Thumb because there is less chance of Thumb equivalent to an ARM instruction. • For a function to be inlined, the last instruction of the function must be either: MOV pc, lr or BX lr A function that consists only of a return sequence can be inlined as a NOP. • A conditional ARM instruction can only be inlined if either: — The condition on the BL matches the condition on the instruction being inlined. For example, BLEQ can only inline an instruction with a matching condition like ADDEQ. — The BL instruction or the instruction to be inlined is unconditional. An unconditional ARM BL can inline any conditional or unconditional instruction that satisfies all the other criteria. An instruction that cannot be conditionally executed cannot be inlined if the BL instruction is conditional. • A BL that is the last instruction of a Thumb-2 If-Then (IT) block cannot inline a 16-bit Thumb instruction or a 32-bit MRS, MSR, or CPS instruction. This is because the IT block changes the behavior of the instructions within its scope so inlining the instruction changes the behavior of the program. Concepts • Handling branches that optimize to a NOP on page 5-21. Using the Assembler: • Conditional instructions on page 6-2. Table 5-1 Inlining small functions ARM ARM 4 to 8 bytes ARM Thumb 2 to 6 bytes Called function size Thumb Thumb 2 to 6 bytes ARM DUI 0474C Copyright © 2010-2011 ARM. All rights reserved. 5-19 ID080411 Non-Confidential
Reference Assembler Reference: • ADD, SUB, RSB, ADC, SBC, and RSC on page 3-50 • B, BL, BX, BLX, and BXJ on page 3-116 • CPS on page 3-140 • MOV and MVN on page 3-61 • MRS on page 3-136 • MSR on page 3-138 • IT on page 3-119. Using linker optimizations ARM DUI 0474C Copyright © 2010-2011 ARM. All rights reserved. 5-20 ID080411 Non-Confidential
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® ARM Copyright © 2010-2011 ARM.
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Contents ARM Compiler toolchain Usi
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Contents 7.15 Creating a symdefs fi
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Chapter 1 Conventions and feedback
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Chapter 2 Overview of the linker Th
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Concepts • Demand paging on page
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2.3 Linker command-line options lis
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• --keep_protected_symbols on pag
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• --eager_load_debug, --no_eager_
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2.5 What the linker outputs 2.5.1 S
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Chapter 3 Linking models supported
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3.2 Bare-metal linking model 3.2.1
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Linking models supported by armlink
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3.5.1 See also • There are restri
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3.7 Concepts common to both BPABI a
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Image structure and generation •
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4.1.1 See also Image structure and
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4.3 Load view and execution view of
Page 37 and 38: 4.4 Methods of specifying an image
Page 39 and 40: 4.5 Types of simple image 4.5.1 See
Page 41 and 42: 4.6.3 See also Image structure and
Page 47 and 48: 4.10 About specifying an initial en
Page 49 and 50: 4.11.2 Example 4.11.3 See also The
Page 51 and 52: 4.13 Section alignment with the lin
Page 53 and 54: Reference Linker Reference: • --a
Page 55 and 56: 4.16 Overview of veneers 4.16.1 See
Page 57 and 58: 4.18 Veneer types 4.18.1 See also I
Page 59 and 60: 4.20 Reuse of veneers when scatter-
Page 61 and 62: 4.22 About weak references and defi
Page 63 and 64: BL init_foo ;Rest of code END 4.22.
Page 65 and 66: Image structure and generation 4.24
Page 67 and 68: 4.25 Specifying user libraries when
Page 69 and 70: 4.27 Use of the strict family of op
Page 71 and 72: 5.1 Elimination of common debug sec
Page 73 and 74: 5.3 Elimination of unused sections
Page 75 and 76: 5.4 Elimination of unused virtual f
Page 77 and 78: • --scatter=file on page 2-142. C
Page 79 and 80: 5.6.1 See also Using linker optimiz
Page 81 and 82: 3. Creates the output image. 5.7.3
Page 83 and 84: 5.9 How the linker chooses a compre
Page 85 and 86: 5.11 How compression is applied 5.1
Page 87: 5.13 Inlining functions with the li
Page 91 and 92: 5.16 About reordering of tail calli
Page 93 and 94: 5.18 About merging comment sections
Page 95 and 96: 6.1 Linker options for getting info
Page 97 and 98: 6.3 Example of using the --info lin
Page 99 and 100: 6.4 How to find where a symbol is p
Page 101 and 102: • Load$$LR$$ load region symbols
Page 103 and 104: 7.2 Accessing linker-defined symbol
Page 105 and 106: 7.4 Image$$ execution region symbol
Page 107 and 108: 7.5.1 See also Accessing and managi
Page 109 and 110: 7.7 Region name values when not sca
Page 111 and 112: 7.9 Importing linker-defined symbol
Page 113 and 114: 7.11 Section-related symbols 7.11.1
Page 115 and 116: 7.13 Input section symbols 7.13.1 S
Page 117 and 118: 7.15 Creating a symdefs file 7.15.1
Page 119 and 120: 7.17 Reading a symdefs file 7.17.1
Page 121 and 122: 7.18.2 See also 0x0000814D T __argv
Page 123 and 124: 7.20 Specifying steering files on t
Page 125 and 126: 7.22 Steering file format 7.22.1 Se
Page 127 and 128: 7.24 Using $Super$$ and $Sub$$ to p
Page 129 and 130: Using scatter files • Images with
Page 131 and 132: 8.2 When to use scatter-loading 8.2
Page 133 and 134: • --startup=symbol, --no_startup
Page 135 and 136: 8.4.1 See also Concepts • About s
Page 137 and 138: 8.5.1 See also } SRAM 0x8000 0x8000
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8.7 Specifying stack and heap using
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8.9 Creating root execution regions
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8.9.2 See also Tasks • Using the
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8.11 Placing functions and data at
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Using scatter files RAM 0x200000 (0
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Using scatter files • Using __at
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Developing Software for ARM ® Proc
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} } .ANY1(+RO) ; evenly distributed
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8.14 Examples of using placement al
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Using scatter files 8.15 Example of
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8.16 Examples of using sorting algo
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8.17 Selecting veneer input section
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Compiler Reference: • __attribute
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8.20 Restrictions on placing __at s
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8.21.1 See also Using scatter files
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8.23 Placing a key in flash memory
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8.25 Placement of sections with ove
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8.25.1 See also Using scatter files
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8.27 Example of placing code in a r
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8.29 Example of placing ARM C++ lib
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8.31 Reserving an empty region Usin
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8.32 About creating regions on page
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8.33 Overalignment of execution reg
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8.35 Expression evaluation in scatt
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8.37 Equivalent scatter-loading des
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Using scatter files Example 8-23 Po
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Using scatter files Example 8-25 Po
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Using scatter files • The ER_ZI e
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Using scatter files Example 8-29 Sc
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Chapter 9 GNU ld script support in
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9.2 Typical use cases for using ld
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Reference Linker Reference: • --l
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9.5 Recommendations for using ld sc
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.data : { __data_start = .; *(.data
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9.6.4 See also .got 0 : { *(.got.pl
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9.7.1 See also } .dynamic : { *(.dy
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9.8.1 See also { *(.bss .bss.*) . =
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Chapter 10 BPABI and SysV shared li
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BPABI and SysV shared libraries and
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10.3 Concepts common to all BPABI m
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10.5 Symbol visibility for BPABI mo
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10.6 Automatic import and export fo
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10.8 Symbol versioning for BPABI mo
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10.10 Linker options for SysV model
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10.13 Addressing modes in the SysV
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10.17 Linker options for bare metal
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10.21 Addressing modes in the BPABI
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10.23 About symbol versioning 10.23
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10.25 Example of creating versioned
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10.27 Linker options for enabling i
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Chapter 11 Features of the Base Pla
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Features of the Base Platform linki
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11.2 Example scatter file for the B
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Features of the Base Platform linki
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Change Topics affected Revisions fo
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