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Hacking the Xbox

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CHAPTER 10<br />

More Hardware<br />

Projects<br />

The similarity of <strong>the</strong> <strong>Xbox</strong> to <strong>the</strong> PC architecture allows hackers to borrow<br />

technology and expertise from <strong>the</strong> PC world when building hardware<br />

projects. As a result, PC hardware, monitors, cables, and peripherals have all<br />

been adapted to work with <strong>the</strong> <strong>Xbox</strong>. This chapter introduces some of<br />

<strong>the</strong>se hardware projects, discovered, documented and implemented by<br />

hackers around <strong>the</strong> world.<br />

The LPC Interface<br />

Version 1.0 of <strong>the</strong> LPC (Low Pin Count) interface was defined by Intel in<br />

1997. The LPC interface is a royalty-free bus that is designed to enable<br />

systems without explicit ISA or X-bus (ISA-like expansion bus for memory<br />

or generic I/O devices) capabilities. The need for <strong>the</strong> LPC interface stems<br />

from <strong>the</strong> large number of low bit-rate, high pin count devices and busses<br />

with incompatible interfaces found in a standard PC, such as <strong>the</strong> floppy<br />

disk, keyboard, mouse, serial, IrDA, parallel, ISA, and boot ROM interfaces.<br />

The aggregate bandwidth consumed by all <strong>the</strong>se devices is small, but <strong>the</strong><br />

number of signals required to support all of <strong>the</strong>m easily exceeds <strong>the</strong> signal<br />

count required by higher-bandwidth buses such as <strong>the</strong> PCI or AGP bus.<br />

Making matters worse, not all configurations of computers requires all of<br />

<strong>the</strong>se legacy I/O devices, and wasted pins and functions just eat away at<br />

profits. The cost of a pin on a chip package is high relative to <strong>the</strong> cost of <strong>the</strong><br />

silicon required to support <strong>the</strong>se simple interfaces. (A rule of thumb is that<br />

one package pin costs a penny, while in 0.13µ silicon, about ten thousand<br />

gates — enough logic to implement a small processor—costs a penny in<br />

silicon area, assuming <strong>the</strong> design is not bond-pad limited 1 .)<br />

The LPC interface counters this problem with a single, low-pin count (seven<br />

required pins, versus <strong>the</strong> 36 pins required for an ISA bus) bus that operates

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