Hacking the Xbox

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226 Hacking the Xbox: An Introduction to Reverse Engineering Design rule checkers are helpful in finding some errors in schematics, but the checks they perform are usually quite elementary, and thus catch only the grossest of errors. A typical set of checks might include catching duplicate part designators, dangling nets, and floating inputs. In addition to conventional design rule checkers, you can also devise your own simple checks. For example, many design tools do not perform “netlist parity checks,” which can be generated fairly easily using a perl script or a spreadsheet program. Netlist parity checks are heuristic checks that tally the number of components connected to each netlist, then sort the tally by the number of connections. The “single-pin nets” will be at the top of the sorted list. A single-pin net is almost always an indication of a typographical error (misspelled netlist name) during schematic capture. It can be useful to browse through the whole sorted list briefly, to see that all groups of signals have the same number of connections. Most signal busses have the same number of connections to every signal in the bus. You can create a tool that enables netlist connection tally checks for your schematic capture program in an afternoon, and you will undoubtedly save yourself countless hours of effort and money by finding the bugs it will catch. Before exporting the schematic to the board layout tool, you should order all of the parts in the schematic’s bill of materials. Often, critical parts will be in short supply and the schematic capture will have to be redesigned to account for the shortage. Frequently, a change in a component footprint assignment is the only redesign necessary. Modifying the schematic design to account for manufacturer’s shortages avoids the difficult task of making the change on a finished board layout. Board Layout The input to a board layout program is a netlist that is annotated with component footprint information. A netlist is an intermediate representation of every component and pin, and their connectivity. Netlist extraction is a well-automated process, but the correlation of schematic symbols to PC board footprints is not always well-managed. The difficulty of symbol-to-footprint correlation stems from the availability of multiple packaging options for a single part. For example, the symbol for a transistor could equally imply a tiny SOT-23 packaged device or an enormous TO-3 packaged device, and it is up to you to ensure that the proper package is chosen during netlist extraction. It’s always good to check the implied footprint when the component is placed in a schematic, rather than checking all at once during the netlist translation, or, worse yet, during placement or final design review. Once you have a finished netlist, you are ready to do the board layout.
Appendix C - Getting Into PCB Layout 227 The other external input to a board layout program are the design rules. Design rules are set by the board fabrication company and include specifications for the minimum trace width and minimum trace to trace spacing, minimum hole size, minimum through-hole annulus, and the number of power and routing layers. The exact design rules depend on the process you choose, which in turn is driven by what you can afford. The best processes offer traces as fine as 2 mils (a mil is 1/1000th of an inch or 25.4 microns) and laser-drilled blind/buried vias with a diameter of about the same, but the price for fabrication is well outside the typical hobbyist’s budget of less than one hundred dollars. A more typical hobbyist’s process features 6 mil trace/space design rules with 15 mil minimum finished hole sizes, with either two or four layers of copper. (You’ll find a list of board fabrication companies toward the end of this appendix.) Board layout consists of two phases: placement and routing. Intelligent parts placement will greatly simplify the routing task. In general, the goal is to place all parts so as to keep connections as short as possible, with as few vias as possible, in order to minimize noise, delay, and signal losses. The placement of some parts, such as connectors, switches, and power components, are well-constrained, leaving you little choice. For the remainder of the parts, an understanding of the design will help you to determine which parts should get the best placement. Once your placement is finished, print the design at a scale of 1:1 and verify that the components fit in their respective footprints by populating the printed layout with the actual components. If you intend to use a socket with a component, be sure to use the socket for verifying the 1:1 plot, as sockets require more space than the component itself. This check guarantees that you have all the components in the correct package type, that all your component outlines are correct, and that there is sufficient clearance between each component to facilitate easy assembly. Another important thing to check on the 1:1 plot is the orientation and pinout of all the connectors because it is very easy to invert a connector or to have used the wrong gender’s footprint on the circuit board. Be careful when handling chips too, especially those with fine-pitch surface mount leads. Be sure not to bend the leads, and observe proper static electricity control protocol. General Placement and Routing Guidelines Here is a short list of some placement and routing guidelines. Remember, these are just general suggestions, and there will undoubtedly be situations where they do not apply.
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Hacking the Xbox An Introduction to
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In memory of Aaron Swartz
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CHAPTER 4 Building a USB Adapter Ca
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Strategy Chapter 4 - Building a USB
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Chapter 4 - Building a USB Adapter
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CHAPTER 5 Replacing a Broken Power
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Chapter 5 - Replacing a Broken Powe
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CHAPTER 8 Reverse Engineering Xbox
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Chapter 8 - Reverse Engineering Xbo
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clearance for motherboard component
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CHAPTER 9 Sneaking in the Back Door
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Note Chapter 9 - Sneaking in the Ba
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CHAPTER 12 Caveat Hacker Reverse en
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