Hacking the Xbox
Hacking the Xbox
Hacking the Xbox
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Appendix D - Getting Started with FPGAs 243<br />
verilog syntax and verilog tutorial are both good sets of keywords to<br />
start out with when searching for syntax references or tutorials. Xilinx’s<br />
website also has a good Verilog reference for FPGA designers, and<br />
Su<strong>the</strong>rland HDL, Inc. has a free Verilog quick reference guide at http://<br />
www.su<strong>the</strong>rland-hdl.com/on-line_ref_guide/vlog_ref_body.html.<br />
Ano<strong>the</strong>r advantage of <strong>the</strong> HDL design entry approach is <strong>the</strong> availability<br />
of free and paid “softcores.” Websites such as www.opencores.org offer<br />
general-public licensed HDL cores for functions such as USB interfaces, DES<br />
and AES crypto-engines, and various microprocessors. In addition, almost<br />
every standard function is offered by third-party vendors who will sell you<br />
cores for a fee.<br />
After design entry, I highly recommended that you simulate your design<br />
before compiling it into hardware. Trying to track down bugs by<br />
twiddling code, pushing it to hardware and probing for changes is very<br />
inefficient. Simulation allows you to probe any node of <strong>the</strong> circuit with<br />
<strong>the</strong> push of a button. In addition, <strong>the</strong> effort required to simulate a code<br />
change is very small, especially when compared to <strong>the</strong> effort of pushing a<br />
change all <strong>the</strong> way through to hardware.<br />
Once <strong>the</strong> design has been entered and simulated, it needs to be compiled or<br />
translated into a common netlist format. This netlist format is fed into a<br />
program that maps <strong>the</strong> netlist primitives into <strong>the</strong> target FPGA hardware<br />
primitives, after which <strong>the</strong> mapped primitives are placed and routed. The<br />
resulting design is analyzed for compliance with a set of constraints<br />
specified by <strong>the</strong> designer. If <strong>the</strong> design does not meet <strong>the</strong> designer’s<br />
specifications, it is iteratively refined through successive place and route<br />
passes. Once <strong>the</strong> design passes its design constraints, it goes to a configuration<br />
bitstream generator where <strong>the</strong> internal representation of <strong>the</strong><br />
FPGA is translated into a binary file that <strong>the</strong> FPGA can use to configure<br />
itself. (All of <strong>the</strong>se steps happen fairly seamlessly at <strong>the</strong> touch of a button<br />
in <strong>the</strong> later versions of <strong>the</strong> FPGA design tools.)<br />
Project Ideas<br />
Now that you know a little bit about what an FPGA is and how you can<br />
program <strong>the</strong>m, what sorts of things can you do with <strong>the</strong>m?<br />
As it turns out, FPGAs have enough logic capacity and performance<br />
<strong>the</strong>se days to accomplish a very impressive range of tasks. The obvious<br />
industrial application of FPGAs is in <strong>the</strong> emulation of designs intended<br />
for hard-wired silicon. The cost of building a custom chip has been<br />
skyrocketing, and it will soon be <strong>the</strong> case where a single critical mistake<br />
can cost hundreds of thousands of dollars, if not millions, to fix.<br />
On <strong>the</strong> o<strong>the</strong>r hand, fixing a mistake made in an FPGA HDL description<br />
pretty much only costs time and design effort; you don’t throw away any<br />
parts, and you don’t have to buy any new parts. Thus, many companies<br />
have adopted <strong>the</strong> strategy of fully simulating a mock-up of <strong>the</strong> design in