Hacking the Xbox

Chapter 2 - Thinking Inside the Box 45
and more. Dividing the PC architecture into these three main modules —
CPU, Northbridge and Southbridge — enables PC designers to mix and
match different kinds of memory architectures with a diverse selection of
processors and peripherals.
The connection between the Northbridge and the Southbridge chipsets
varies from chipset to chipset. In the case of the Xbox, a high performance,
narrow parallel bus called HyperTransport is employed as the
connection between the functional equivalent of the Northbridge and
Southbridge chips. The bus is only 8 bits wide in each of two directions,
but it is clocked at 200 MHz and data is sampled on each clock edge so
the effective peak transfer rate is 400 Mbytes/second in each direction. A
Northbridge chip is connected to a CPU via a bus called the Front Side
Bus (FSB). In the case of the Xbox, the FSB is a 64-bit 133 MHz bus that
uses AGTL+ logic levels.
Knowing and understanding the kinds of connections between chips is
crucial in reverse engineering because the kind of connection will dictate
how difficult it is to intercept data going between various components.
The details of the relatively easier bus to tap, the HyperTransport bus, are
discussed in Chapter 8, “Reverse Engineering Xbox Security.”
In the Xbox, the Southbridge is a chip designed by nVidia called the
MCPX; it is a derivative of the nVidia nForce MCP Multimedia and
Communications Processor. The Northbridge chip was also designed by
nVidia, and it is called the NV2A GPU. Both the Northbridge and
Southbridge chips were manufactured by TSMC (Taiwan Semiconductor
Manufacturing Corporation). The NV2A combines both a GPU (Graphics
Processing Unit) and the traditional memory and expansion bus
controllers found in most Northbridge chips. As explained previously,
combining the graphics processor and the Northbridge allows system
designers to merge the graphics memory into main memory, at some
performance penalty.
RAM
The Xbox motherboard employs 64 MB of DDR SDRAM for the main
memory. DDR SDRAM stands for Double Data-Rate Synchronous
Dynamic Random Access Memory. By combining synchronization and
DDR techniques, the aggregate bandwidth of the Xbox main memory
achieves 6.4 Gigabytes/second.
A RAM is basically a table of information that is indexed by the CPU.
Each location in RAM has a unique index number called its address, and
as the name “random access” implies, there are no restrictions on the
order of data access in a RAM. 1
1 Actually, SDRAMs can have a few restrictions on memory access
patterns (such as page modes and burst modes) for performance
reasons. The “random” moniker is intended to differentiate RAMs
from First-In, First-Out (FIFO) and Last-In, First-Out (LIFO) style
memories where data is accessed using a strict set of ordering
rules.