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Hacking the Xbox

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264<br />

<strong>Hacking</strong> <strong>the</strong> <strong>Xbox</strong>: An Introduction to Reverse Engineering<br />

LPC Connector<br />

The <strong>Xbox</strong> features a debug and test port based on <strong>the</strong> LPC (Low Pin<br />

Count) bus. This bus was originally defined by Intel for use with<br />

Southbridge chipsets to reduce pin count, thus saving on cost, while<br />

maintaining support for legacy PC I/O functions. These legacy I/O<br />

functions used to sit on <strong>the</strong> nearly extinct ISA bus, and <strong>the</strong>y include <strong>the</strong><br />

keyboard, mouse, serial port, parallel port, and boot ROM. Intel’s specification<br />

for <strong>the</strong> LPC bus can be found at http://www.intel.com/design/<br />

chipsets/industry/25128901.pdf.<br />

The LPC debug connector is particularly significant because it can be used to<br />

supply an alternate ROM image to <strong>the</strong> <strong>Xbox</strong> in case <strong>the</strong> built-in ROM is<br />

absent or corrupted in a fashion that makes <strong>the</strong> ROM seem absent or blank.<br />

This feature can be and has been used to make an easy to install alternate<br />

boot ROM for <strong>the</strong> <strong>Xbox</strong>.<br />

The pinout for <strong>the</strong> <strong>Xbox</strong> LPC debug connector seems to be based on <strong>the</strong><br />

Installable LPC Debug Module Design Guide by Intel, http://<br />

www.intel.com/technology/easeofuse/LPC_mod_spec72.pdf,<br />

with some minor modifications as noted in Table F-7. In particular, <strong>the</strong><br />

function of pin 16 is unclear, as its companion pin 15 was re-assigned to be<br />

a power pin on <strong>the</strong> <strong>Xbox</strong> mo<strong>the</strong>rboard. The allocation of pin 15 as a power<br />

pin is deduced by <strong>the</strong> fat trace and nearby decoupling capacitor allocated to<br />

<strong>the</strong> pin. If pin 15 were intended for use as a permanently high SPDA1<br />

signal, <strong>the</strong>n a narrower trace without <strong>the</strong> power conditioning would have<br />

been used.<br />

Pin Name Comment Pin Name Comment<br />

1 LCLK 33 MHz clock<br />

Start, end of LPC<br />

2 VSS Current return<br />

3 LFRAME# transactions 4 KEYWAY Blank for polarizing<br />

5 LRST# LPC Reset 6 VCC5 +5V power<br />

7 LAD3# Muxed Address/Data 8 LAD2# Muxed Address/Data<br />

9 VCC3 +3.3V power 10 LAD1# Muxed Address/Data<br />

11 LAD0# Muxed Address/Data 12 VSS Current return<br />

13 SCL I2C serial clock 14 SDA I2C serial data<br />

+3.3V power (was<br />

Address select for serial<br />

15 VCC3 SPDA1 in Intel spec.) 16 SPDA0 EEPROM device (?).<br />

Table F-7: LPC connector pinout (as viewed on mo<strong>the</strong>rboard).

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