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Hacking the Xbox

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230<br />

<strong>Hacking</strong> <strong>the</strong> <strong>Xbox</strong>: An Introduction to Reverse Engineering<br />

The proper sizing of a power trace depends upon <strong>the</strong> thickness of <strong>the</strong><br />

copper. Typical boards use “1-oz copper” that is 1.35 mils thick (one square<br />

foot of 1.35 mil thick copper foil weights one ounce). An exterior 12 mil<br />

wide trace in 1 oz copper is required to pass 1 ampere of current with a 10<br />

degree Celsius temperature rise. Thicker traces are required for buried layers<br />

for a similar current handling capacity.<br />

When routing power traces between layers, remember that vias have<br />

resistance as well. A single via is insufficient to connect critical power traces<br />

between layers. Critical power traces should have multiple vias connecting<br />

<strong>the</strong>m between layers to keep parasitic resistances and inductances down.<br />

Distributed power planes on multiple layers should also have vias generously<br />

distributed throughout to ensure that a common potential is<br />

preserved.<br />

Note<br />

In high performance or low noise applications, placing a<br />

via between a decoupling capacitor and <strong>the</strong> power pin<br />

may carry too high an electrical integrity price for <strong>the</strong><br />

routing convenience. Vias disrupt <strong>the</strong> propagation of highspeed<br />

(hundreds of megahertz) electrical waves. Thus,<br />

<strong>the</strong> optimal location of a decoupling capacitor in <strong>the</strong>se<br />

applications is between <strong>the</strong> component pin and <strong>the</strong> power<br />

via.<br />

Timing reference signals include clocks and strobes. Many memory devices<br />

require asynchronous control strobes that have sensitive timing requirements.<br />

These signals should be properly terminated and routed in a manner<br />

consistent with <strong>the</strong> termination strategy, typically a “daisy chain” route. Daisy<br />

chain routes have no branches, so <strong>the</strong>re is only one path for <strong>the</strong> wavefront<br />

of <strong>the</strong> signal to travel.<br />

Electric signals travel at about 1/4 <strong>the</strong> speed of light on a circuit board, or<br />

about three inches in a nanosecond. Thus, high speed traces must have<br />

matched lengths, or signals can arrive significantly out of phase with respect<br />

to <strong>the</strong> timing reference. Trace lengths are matched by extending shorter traces<br />

to <strong>the</strong> length of <strong>the</strong> longest trace. Trace length extension is accomplished<br />

using serpentine traces that meander and increase <strong>the</strong> effective length of a<br />

trace without changing <strong>the</strong> placement of <strong>the</strong> trace’s endpoints.<br />

Analog and mixed-signal routing is well beyond <strong>the</strong> scope of this appendix.<br />

In an average hobbyist’s digital design, most of <strong>the</strong> analog circuitry will be<br />

isolated to <strong>the</strong> power supplies. Any special layout requirements for a<br />

particular power supply component is typically well-documented in <strong>the</strong><br />

component’s datasheet.<br />

Keep in mind that electrical signals are lazy and promiscuous: signal<br />

current will always follow <strong>the</strong> path of least resistance, and signals will<br />

couple into adjacent traces. Fur<strong>the</strong>rmore, current must be conserved, so<br />

every signal current path must have a return current path, whe<strong>the</strong>r it is<br />

explicit or not. Keep <strong>the</strong>se simple rules in mind as you layout any analog<br />

sections on your circuit board.

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