RK06/RK07 Disk Drive User's Manual - Trailing-Edge

Controller Modifications - In Diagnostic mode, the operation of the controller is modified by disabling
the generation of certain error and control signals, while simulating and monitoring the generation of
other signals, as follows.
Generation of these error conditions is inhibited:
1. Controller Time-Out (CTO) (bit 11 in RKCS1)
2. Programming Error (PGE) (bit 10 in RKCS2)
3. Unit Field Error (UFE) (bit 13 in RKCS2)
4. Drive Timing Error (DTE) (bit 12 in RKER)
Generation of these signals is simulated:
1. Index Pulse (MIND)
2. Sector Pulse (MSP)
3. Data/Control Clock (MCLK)
4. Read Data (MERD)
5. Even Parity (PAT) on Messages A and B (can only be done in real-time).
These signals are monitored:
1. Precompensation Advance (PCA)
2. Precompensation Delay (PCD)
3. Timing in ECC area of sector (ECCW)
4. Write Data (MEWD)
5. Read Gate (RD)
6. Write Gate (WRT)
Timing Considerations - The Maintenance Clock (MCLK) bit (bit 8 in RKMR1) can be alternately set
and reset (by repeatedly loading RKMR 1) to provide a program-controlled clock. Pulses generated by
M CLK replace the data clock, used to control the transfer of data bits to and from the
Encoder /Separator logic, and to generate control clock, used to synchronize message shifting operations.
Predicating the generation of controller timing on the system clock allows a diagnostic program
to monitor response conditions following the initiation of each write operation to RKMR 1.
For the proper simulation of data transfers in Diagnostic mode, the following timing considerations
must be adhered to (Figure 7-29).
7-30