RK06/RK07 Disk Drive User's Manual - Trailing-Edge

Error
Operation Incomplete (OPI)
DTC Parity Error (DTC
PAR)
Write Check Error (WCE)
Nonexistent Memory
(NEM)
Data Late Error (DLTERR)
Drive Timing Error (DTE)
Data Check (DCK)
Multiple Drive Select (M DS)
Error Correction Hard (ECH)
Controller Time-Out (CTO)
Table 7-1 Combined Error (CERR) (Cont)
Indicator Bit
RKER bit 13
RKCSI bit 13
RKCS2 bit 14
RKCS2 bit 11
RKCS2 bit 15
RKER bit 12
RKER bit 15
RKCS2 bit 9
RKER bit 6
RKCSI bit II
Condition
Desired header cannot be found.
Parity error in message from drive.
Write Check indicates data from disk
did not match data from memory.
No SSYN within 10 JlS of MSYN assertion.
Data late to /from Silo.
Write Clock loss during write, data
loss during read.
Data error detected by ECC.
More than one drive simultaneously
selected.
Data error un correctable using ECC.
Command possibly not executed.
7.2.2 Word Count Register (RKWC)
The RK WC register (Figure 7-3) is loaded with the two's complement of the number of data words to
be transferred to or from main memory. The register is incremented by 1 after each bus cycle, and
accommodates a maximum transfer of 65,536 words. The RKWC register can only be cleared by
writing all zeros via program control.
7.2.3 Bus Address Register (RKBA)
The RKBA register (Figure 7-4) is initially loaded with the low-order 16 bits of the Unibus address
that will reflect the main memory start location for a data transfer. With the low-order bit (0) always
forced to 0, the RKBA register content is combined with high-order bits 8 and 9 of the RKCS 1 register
(BA 16, BAI7) to form a complete even-numbered word address. Following each data transfer bus
cycle, the register is incremented by two to select the next even-numbered location.
7.2.4 Disk Address Register (RKDA)
For Read, Write, and Write Check commands, the RKDA register (Figure 7-5) is initially loaded to
define the desired sector (1 of 20 or 22) and track (l of 3 read/write heads) on the selected drive, from
or to which the first block of a data transfer will be initiated. If the word count value indicates that a
block of more than 256 data words is to be transferred, the Sector Address bits of the RKDA register
will be incremented to select the next consecutive sector and the next track, if necessary, until a word
count overflow indicates that data transfers are completed or an error occurs. In either case, completion
of the command is indicated by the setting of the Controller Ready (RDY) bit in RKCS 1 and
an increment of the RKDA register to the next sector location.
Sector Address Bits 0-4 (SAO-SA4)
Sector Address bits 0-4 are configured (00-23) to select a value (00-19 19) for a 20-sector format (18-bit
data words) or configured (00-25) to select a value (00-2119) for a 22-sector format (l6-bit data words).
The Sector Address is incremented by one when the sector has been transferred.
7-6