Chapter 03 Power, Reset, and Clock Management.pdf

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CLK Power domain Ctrl Voltage domain VDD1 CLK1 Vmemory Clock domain CLK1 Public Version Introduction to Power Managements www.ti.com Figure 3-8. Voltage, Power, and Clock Domain Hierarchical Architecture Voltage control Secondary switch Ctrl Voltage regulator VDD1 CLK2 Clock domain CLK2 Primary switch Non-retention logic Retention logic Each power domain is supplied by one or more voltage domains that can be scaled down or switched off to save power. Internal memory and logic can be put in standby (retention) mode independently. In this state, memory is not operational, but the content is retained with minimized leakage. This feature lets power consumption be reduced when the device is in sleep mode while maintaining memory contents for fast context restore. The logic and memory standby feature is software-controllable. The device supports a clock distribution and control architecture, which is described in the following sections. 3.1.4.1 Module Interface and Functional Clocks The clocks delivered to the modules in the device are divided into two categories: interface clocks and functional clocks (see Figure 3-9). 232 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-008
Interface clocks Clock generator Functional clocks { Public Version www.ti.com Introduction to Power Managements Figure 3-9. Functional and Interface Clocks Interconnect X_FCLK Interface clocks have the following characteristics: X_ICLK Module X Y_ICLK Y_FCLK Module Y • They ensure proper communication between any module/subsystem and the interconnect. • In most cases, they supply the module interface and registers. • A typical module has one interface clock, but it can have several. • They are synchronous across the entire device, because the interconnect fabric is fully synchronous. • Interface clock management is done at the device level. • From the standpoint of the PRCM module, an interface clock is distributed through the device interconnect and is identified with an _ICLK suffix. Functional clocks have the following characteristics: • They supply the functional part of a module or a subsystem. • Each module can have several functional clocks, or none. A module may or may not require its functional clocks to be active (nonidle). • Several modules can share the same functional clock signals, but the branches of the clock tree are not balanced among the modules. • From the PRCM module standpoint, a functional clock is directly distributed to the related modules through a dedicated clock tree. It is identified with an _FCLK suffix. NOTE: At the module level, the interface clocks are always fed by the interface clock outputs of the PRCM module. The functional clocks are fed by a PRCM functional clock output or a PRCM interface clock output. In the latter case, the functional and interface clocks of the module inherit capabilities (autoidle features) from the PRCM interface clock (see Section 3.5.3, Clock Manager Functional Description). 3.1.4.2 Autoidle Clock Control The device supports an autoidle clock control scheme for the module interface clocks. With this control scheme, the PRCM module can automatically activate and deactivate the interface clock of any device module, depending on its operating mode. This scheme executes under hardware control and is transparent to the software. This scheme identifies two module types in the device: the target and the initiator modules, or subsystems. NOTE: The functional clocks do not have the autoidle clock scheme, and the software must gate the functional clock of each module when it is not needed. Initiator SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated prcm-009 233
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