Chapter 03 Power, Reset, and Clock Management.pdf

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MPU domain Microprocessor domain NEON domain Multimedia coprocessor domain PER domain Low power uses cases peripherals domain DSS domain Display domain EFUSE domain eFuses FARM domain USBHOST domain DPLL1 domain MPU DPLL domain DPLL4 domain Peripherals DPLL domain Public Version PRCM Integration www.ti.com Figure 3-18. Device Power Domains WKUP domain Wake-up domain (always active) DPLL power domains DPLL5 domain Peripherals DPLL2 domain IVA2 domain Audio video processor domain CORE domain Interconnect, memory controllers, peripherals and clock management domain SGX domain Graphics engine domain CAM domain Camera controller domain SMARTREFLEX domain SmartReflex engine domain EMU domain Emulation domain DPLL2 domain IVA2 DPLL domain DPLL3 domain CORE DPLL domain Each power domain is fed through an independent switch controlled by the PRM module. In this way, depending on the application scenario, unused parts (domains) can be switched off or put in retention state while others remain active. 246 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-017
Public Version www.ti.com PRCM Integration 3.4.1 Power-Management Scheme, Reset, and Interrupt Requests 3.4.1.1 Power Domain The PRCM module is in two power domains (see Table 3-5). Table 3-5. PRCM Power Domains PRCM Subsystem Modules Power Domain PRM WKUP CM CORE The PRM module is in the WKUP power domain, which is continuously active. It is composed of the logic that must be permanently supplied to manage domain power-state transitions and detect wake-up events. The CM module is in the CORE power domain, which can be activated and deactivated according to the requirements of the executing applications. 3.4.1.2 Resets The PRM and CM modules are reset by independent reset signals (see Table 3-6). Table 3-6. PRCM Reset Signals PRCM Subsystem Reset Signal PRM PRM_RSTPWRON CM CM_RSTPWRON_RET The PRM module is reset by the cold reset signal PRM_RSTPWRON. The CM module is reset by assertion of the CM_RSTPWRON_RET signal. The CM logic is reset on: • Any global cold reset • A CORE power domain transition from off to on The PRM logic is reset on any global cold reset. CM and PRM registers that are sensitive to a warm reset are also reset when a global warm reset occurs. However, the CM and PRM logic is not reset. NOTE: At global cold reset: • Only the device finite state-machine (FSM) in the PRM operates on the 32-kHz clock, and it is released from reset on the release of the global reset. • PRM logic operates on the system clock and is released from reset on release of the reset PRM_RSTPWRON. Figure 3-19 shows the PRCM reset signals. SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated 247
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