Chapter 03 Power, Reset, and Clock Management.pdf

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PRCM Functional Description www.ti.com
2. Software clears the PRCM.RM_RSTCTRL_IVA2[1] RST2_IVA2 bit. The PRM module releases the
IVA2_RSTPWRON reset signal when reset manager 2 in the IVA2 power domain times out.
3. On release of IVA2_RSTPWRON, the IVA2.2 subsystem performs an initialization sequence.
4. The IVA2.2 subsystem asserts the IVA2_RST_DONE signal when initialization completes.
5. The PRM module releases the IVA2_RST2 reset signal.
6. The PRCM.RM_RSTST_IVA2[9] IVA2_SW_RST2 status bit is updated accordingly on release of the
IVA2_RST2 reset signal. The MPU software can now program the MMU or download the DSP code.
7. Software clears the PRCM.RM_RSTCTRL_IVA2[0] RST1_IVA2 bit. The PRM module waits for reset
manager 1 in the IVA2 power domain to time out.
8. The PRM module releases the IVA2_RST1 reset signal. The DSP boots.
9. The PRCM.RM_RSTST_IVA2[8] IVA2_SW_RST1 status bit is updated accordingly on release of the
IVA2_RST1 reset signal.
10. DSP software enables the video sequencer (SEQ) clock.
11. DSP software clears the PRCM.RM_RSTCTRL_IVA2[2] RST3_IVA2 bit. The PRM waits for reset
manager 3 in the IVA2 power domain to time out.
12. After reset manager 3 times out, the PRM can release the IVA2_RST3 reset signal. The SEQ boots.
13. The PRCM.RM_RSTST_IVA2[10] IVA2_SW_RST3 bit is updated accordingly on release of the
IVA2_RST3 reset signal.
3.5.1.9.4 IVA2 Software Reset Sequence
This section describes the software reset sequence and timing relationships of the IVA2.2 subsystem.
The assumptions are:
• The MPU is running.
• All sources of reset to the IVA2.2 subsystem are released.
• The software ensures that the IVA2.2 subsystem software sources of reset are not asserted while the
IVA2 power domain clocks are running.
• The software clears the previous reset status.
Figure 3-31 shows the IVA2 software reset sequence.
272 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011
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