Chapter 03 Power, Reset, and Clock Management.pdf

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3.5.1.5 Power Domain Reset Descriptions
3.5.1.5.1 MPU Power Domain
The MPU power domain has two reset input signals and one reset output signal (see Table 3-9).
Name I/O (1)
Table 3-9. MPU Power Domain Reset Signal
Source/Destination (2)
Reset Domain
MPU_RST I PRM Resets the MPU processor core and the
asynchronous bridge in the MPU power domain
(1)
I = Input; O = Output
(2)
Source for an input signal and destination for an output signal
3.5.1.5.2 NEON Power Domain
The NEON power domain has one reset input signal (see Table 3-10).
Table 3-10. NEON Power Domain Reset Signal
Name I/O (1) Source Reset Domain
NEON_RST I PRM Resets the NEON coprocessor
(1) I = Input; O = Output
3.5.1.5.3 IVA2 Power Domain
The IVA2 power domain has four inputs and one output reset signal (see Table 3-11).
Table 3-11. IVA2 Power Domain Reset Signals
Name I/O (1) Source/Destination (2) Reset Domain
IVA2_RST1 I PRM Resets the IVA2.2 DSP and part of the two
asynchronous bridges in the IVA2 power domain
IVA2_RST2 I PRM Resets the IVA2.2 MMU
IVA2_RST3 I PRM Resets the video sequencer module
IVA2_RSTPWRON I PRM Performs a power-on reset on the IVA2.2 subsystem.
Active on a cold reset only.
IVA2_RSTDONE O PRM Release condition of the IVA_RST1 and RST2.
Generated by the IVA2.2 subsystem at the end of the
initialization sequence.
(1) I = Input; O = Output
(2) Source for an input signal and destination for an output signal
3.5.1.5.4 CORE Power Domain
The CORE power domain has eight inputs and one output reset signal (see Table 3-12).
Table 3-12. CORE Power Domain Reset Signals
Name I/O (1) Source/Destination (2) Reset Domain
CORE_RST I PRM Resets parts of the three asynchronous bridges, MPU
INTC, IVA2.2 WUGEN, interconnects, ICR, modem
INTC, SAD2D, mailboxes, GPMC, OCM, UART[1,2],
HDQ, HS USB, I2C[1..3], McBSP 1 and 5, McSPI [1..3],
MMC[1..3], GPTIMER[10,11]
CORE_RST_RET I PRM Resets part of the SDRC, SDMA, SMS, MPU INTC, and
IVA2 WUGEN
CORE_RSTPWRON_RE I PRM Resets part of the SDRC and SCM
T
CM_RSTPWRON_RET I PRM Resets the clock manager
(1)
I = Input; O = Output
(2)
Source for an input signal and destination for an output signal
254 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011
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