Chapter 03 Power, Reset, and Clock Management.pdf

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Domains voltages Device PRCM VDD3 Ctrl VDD1 VDD2 VDD4 VDD5 LDO LDO sys_nreswarm sys_nrespwron sys_32k sys_xtalout sys_xtalin sys_altclk sys_boot6 sys_clkreq sys_clkout1 sys_clkout2 sys_nvmode1 /i2c4_scl sys_nvmode2 /i2c4_sda sys_off_mode Public Version PRCM Environment www.ti.com 3.3 PRCM Environment The PRCM module receives the external reset, clock, and power signals. Figure 3-12 shows the interface of the PRCM module with external reset, clock, and power sources. Figure 3-12. PRCM Functional External Interface (Detailed View) 1.8 V Pullup vdd_mpu_iva vdd_core To peripherals Reset button To peripherals vdda_wkup_bg_bb vdda_sram Power IC NOTE: In the remainder of this chapter, "power IC" refers to a peripheral power source IC that is interfaced with the device. It receives power control commands (voltage scaling and power switching) from the device and provides the necessary voltages and reset signals. 240 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-011
PRCM PRM CM Public Version www.ti.com PRCM Environment The following sections describe the interfaces for external clock, reset, and power sources. 3.3.1 External Clock Signals The device has three external clock inputs: low frequency (sys_32k), high frequency (sys_xtalin), and an optional clock (sys_altclk). The device has two configurable clock outputs: sys_clkout1 and sys_clkout2. Figure 3-13 shows the external clock signals of the PRCM module. Table 3-2 lists the external clock signals, I/Os, and module reset values. Figure 3-13. External Clock Interface Device sys_boot6 sys_32k sys_xtalout sys_xtalin sys_clkreq sys_clkout1 sys_altclk sys_clkout2 Table 3-2. External Clock Signals Signal I/O (1) Description Module Reset Value sys_boot6 I Boot oscillator mode control Unknown (2) sys_32k I 32-kHz clock input Unknown (3) sys_xtalout O Oscillator output 0 sys_xtalin I Main input clock. Crystal oscillator clock (only at 12, 13, 16.8, or 19.2 Unknown MHz) or CMOS digital clock (at 12, 13, 16.8, 19.2, 26, or 38.4 MHz). sys_clkreq I/O Clock request to/ from device for system clock HiZ/1 (4) sys_clkout1 O Configurable output clock 1 0 sys_altclk I Additional selectable clock source Unknown (5) sys_clkout2 O Configurable output clock 2 0 (1) I = Input; O = Output (2) sys_boot6 is either powered down or powered up (3) Reset cannot be released without 32K stable and running (4) sys_clkreq depends on sys_boot6 (5) sys_altclk is not enabled by default SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated prcm-013 241
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