Chapter 03 Power, Reset, and Clock Management.pdf

Public Version
PRCM Functional Description www.ti.com
Type (1)
Table 3-7. Global Reset Sources (continued)
Name Source/Control Description
H/W MPU_WD_RST WDTIMER2 MPU watchdog timer overflow reset
S/W GLOBAL_SW_RST PRCM.PRM_RSTCTRL[1] RST_GS Global software reset
H/W VDD1_VM_RST PRCM Asserted by the voltage manager FSMs
H/W VDD2_VM_RST PRCM
when no response from the power IC is
received during wake-up transition from
retention or off mode
S/W DPLL3_SW_RST PRCM.PRM_RSTCTRL[2] Local cold reset for DPLL3 and a global
RST_DPLL3 cold reset to the device
3.5.1.3.2 Local Reset Sources
Table 3-8 lists the local reset sources of the device. A local reset source signal received by the reset
manager resets only some of the device modules.
Table 3-8. Local Reset Sources
Type (1) Name Source/Control Description
H/C CORE_DOM_RET_RST PRCM Asserted only for a power domain
H/C USB_DOM_RET_RST PRCM
state transition from off to active
state
H/C PER_DOM_RET_RST PRCM
H/C MPU_DOM_RST PRCM Asserted for any power domain
transition from off or retention
state to active state
H/C IVA2_DOM_RST PRCM
H/C NEON_DOM_RST PRCM
H/C SGX_DOM_RST PRCM
H/C CORE_DOM_RST PRCM
H/C PER_DOM_RST PRCM
H/C CAM_DOM_RST PRCM
H/C DSS_DOM_RST PRCM
H/C DPLL1_DOM_RST PRCM
H/C DPLL2_DOM_RST PRCM
H/C DPLL3_DOM_RST PRCM
H/C DPLL4_DOM_RST PRCM
H/C DPLL5_DOM_RST PRCM
S/W IVA2_SW_RST1 PRCM.RM_RSTCTRL_IVA2[0] IVA2.2: DSP reset control
RST1_IVA2
S/W IVA2_SW_RST2 PRCM.RM_RSTCTRL_IVA2[1] IVA2.2: MMU reset control and
RST2_IVA2 video sequencer hardware
accelerator reset control
S/W IVA2_SW_RST3 PRCM.RM_RSTCTRL_IVA2[2] Video sequencer reset control
RST3_IVA2
(1) H = Hardware reset, S = Software reset, C = Cold reset, W = Warm reset
NOTE:
• For power domains with domain name_DOM_RST and domain name_DOM_RET_RST,
the reset sources are asserted together when the domain transitions from off to on
power state, whereas only domain name_DOM_RET_RST is asserted on a global or
local warm reset.
• Because the modem reset signals are not supported in the device stand-alone
configuration, they are not discussed in this section.
252 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated