Chapter 03 Power, Reset, and Clock Management.pdf

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Signal color-coding PRCM input PRCM output Other vdds, vdda_wkup_bg_bb, vdds_mem, vdda_sram vdda_dpll_dll, vdda_dpll_per VDD3 voltage domain vdd_core vdd_mpu_iva VDD4 voltage domain VDD5 voltage domain sys_32k OSC_CLK sys_nrespwron sys_nreswarm_out Global power on reset Global warm reset SYS_CLK EFUSE_RSTPWRON PRM_RSTPWRON CM_SYS_CLK CM_RSTPWRON_RET DPLL[1,2,3,4,5]_ RSTPWRON DPLL3_ALWON_FCLK L3_ICLK CORE_RST DPLL1_ALWON_FCLK MPU_CLK MPU_RST Public Version PRCM Functional Description www.ti.com 3.5.1.9 Reset Sequences 3.5.1.9.1 Power-Up Sequence Figure 3-28 shows the power-up sequence. Figure 3-28. Power-Up Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 266 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-096
Public Version www.ti.com PRCM Functional Description The power-up sequence shown in Figure 3-28 is: 1. Voltages ramp up and global power-on reset is asserted by the external power IC: • vdds, vdds_mem, vdda_wkup_bg_bb, vdda_sram voltage rails are ramped up. • sys_nrespwron is asserted (set to low). • vdda_dpll_dll and vdda_dpll_per voltage rails are ramped up before release of sys_nrespwron (transition to high). • The VDD3 voltage domain LDO (WKUP power domain) tracks vdda_wkup voltage rail and automatically ramps up. • After VDD3 voltage domain stabilization, the power IC ramps up VDD2 voltage domain. • After VDD2 voltage domain stabalization, the power IC ramps up VDD1 voltage domain. 2. Source clock stabilizes: • The 32-kHz input clock and the system clock oscillator stabilize. • The device reset manager holds the entire device under reset. • The system clock (SYS_CLK) is on. 3. The global power-on reset sys_nrespwron released (to high) when vdda_dpll_dll and vdda_dpll_per voltage rails are stabilized. 4. The eFuse farm reset is released. 5. Internal memory LDOs ramp up: • Processor memory LDO (VDD4 voltage domain) is ramped up. • CORE memory LDO (VDD5 voltage domain) is ramped up. • The PRCM module waits for internal memory LDO stabilization. 6. Global resets are released. Global power-on reset and global warm reset are extended (remain asserted) on release of the external power-on reset until the following conditions are met: • Voltages are stable in the processor power domains, CORE power domain, and WKUP power domain. • System clock is stable. • Internal memory LDO is stable. • Device reset manager counter overflows (set up by the PRCM.PRM_RSTTIME[7:0] RSTTIME1 bit field). • Hardware conditions, such as eFuse farm ready, are set. 7. The PRM_RSTPWRON reset is released. 8. The CM_SYS_CLK clock starts running (gating logic is enabled). 9. The CM_RSTPWRON_RET reset is released. 10. The reset of the DPLLs is released. 11. The DPLL3_ALWON_FCLK clock starts to run (gating logic is enabled). 12. The L3_ICLK clock starts to run. 13. The DPLL1_ALWON_FCLK clock starts to run (logic controlling the clock-gating conditions element is clocked and the clock is requested). 14. The CORE_RST reset is released. 15. The MPU_CLK clock starts to run. 16. The MPU boots. NOTE: • The IVA2 power domain is held under reset after power up by assertion of the software source of reset. • Power domains such as DSS, CAM, SGX, and NEON are held under reset after power up until the MPU software enables the power domain interface clocks. SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated 267
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