Chapter 03 Power, Reset, and Clock Management.pdf

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BAD_DEVICE_RST Global warm reset MPU_DOM_RST CORE_DOM_RET_RST NEON_DOM_RST CORE_DOM_RET_RST IVA2_SW_RST1 IVA2_DOM_RST CORE_DOM_RET_RST IVA2_SW_RST2 IVA2_DOM_RST CORE_DOM_RET_RST IVA2_SW_RST3 IVA2_DOM_RST CORE_DOM_RET_RST SGX__DOM_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RST Public Version PRCM Functional Description www.ti.com Figure 3-25. Power Domain Reset Management: Part 1 MPU domain reset manager NEON domain reset manager IVA2 domain reset manager 1 IVA2 domain reset manager 2 IVA2 domain reset manager 3 SGX domain reset manager CORE domain reset manager 1 CORE domain reset manager 2 CORE domain reset manager 4 MPU_RST NEON_RST IVA2_RST1 IVA2_RST2 IVA2_RSTPWRON IVA2_RST3 SGX_RST CORE_RST CORE_RST_RET CORE_RSTPWRON_RET USBTLL_RST 260 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-024
Global power on reset CM reset CORE_DOM_RET_RST manager Global warm reset BAD_DEVICE_RESET DSS_DOM_RST CORE_DOM_RET_RST CAM_DOM_RST CORE_DOM_RET_RST PER_DOM_RST CORE_DOM_RET_RST PER_DOM_RET _RST CORE_DOM_RET_RST USB_DOM_RST CORE_DOM_RET_RST Public Version www.ti.com PRCM Functional Description Figure 3-26. Power Domain Reset Management: Part 2 DSS domain reset manager CAM domain reset manager PER domain reset manager 1 PER domain reset manager 2 USBHOST domain reset manager CM_RSTPWRON_RET DSS_RST CAM_RST PER_RST PER_RST_RET USBHOST_RST SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated prcm-025 261
Page 1 and 2: Public Version Chapter 3 SPRUGN4L-M
Page 3 and 4: Normalized frequency 1.5 1.0 0.5 0
Page 5 and 6: Public Version www.ti.com Introduct
Page 7 and 8: Ctrl CLK1 Subsystem A Subsystem B C
Page 9 and 10: Voltage control Subsystem A Voltage
Page 11 and 12: Interface clocks Clock generator Fu
Page 13 and 14: SmartReflex functional clock Interr
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Page 23 and 24: Device Power control logic Retentio
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Page 27 and 28: Generic power domain Reset domain 1
Page 29 and 30: Device Reset sources MPU watchdog (
Page 31 and 32: Device Reset destinations IVA2 WKUP
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Page 35 and 36: PRCM PRM Device sys_nreswarm_out sy
Page 37: GLOBAL_SW_RST DPLL3_SW_RST VDD1_VM_
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Page 71 and 72: MPU_CLK IVA2_CLK L4_ICLK L3_ICLK 96
Page 73 and 74: sys_clkout1 sys_clkreq sys_xtalout
Page 75 and 76: PRM_192M_ALWON_CLK Public Version C
Page 77 and 78: DPLL_FCLK DPLL_ALWON_FCLK PRCM DPLL
Page 79 and 80: WKUP power domain PRM DPLL3_ALWON_F
Page 81 and 82: DPLL_FCLK DPLL_ALWON_FCLK PRCM DPLL
Page 85 and 86: MPU power domain MPU subsystem WKUP
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From system control module MCBSP_CL
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PRM Public Version www.ti.com PRCM
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CORE power domain CM 96M_FCLK L3_IC
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WKUP power domain PRM WKUP L4 inter
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Public Version www.ti.com PRCM Func
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sys_xtalout sys_xtalin sys_boot6 sy
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DPLL3_ALWON_FCLK DPLL4_ALWON_FCLK s
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CORE_CLK SYS_CLK Source selection/d
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CM_SYS_CLK CM_32K_CLK 120M_FCLK OSC
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DPLL4_ALWON_FCLK 120M_FCLK 48M_FCLK
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96M_ALWON_FCLK 48M_FCLK SYS_CLK 32K
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SYS_CLK L4_ICLK Public Version www.
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Device power consumption OFF Switch
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1 2 3 4 5 6 Functional Functional c
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SYS_CLK Device state sys_nvmode2 VD
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SR_ALWON_FCLK PRM VDD1 error VDD1 v
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SmartReflex module: error SmartRefl
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Public Version www.ti.com PRCM Basi
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Selected source clock CM_POLCTRL [0
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sys_32k SYS_CLK WKUP Event sys_clkr
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Enable module functional clock Modu
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Enable module interface clock Modul
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Device power on 5. Interrupt genera
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Device 2. Voltage 3. Command config
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Frequency scaling when target OPP f
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Public Version www.ti.com PRCM Regi
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Chapter 03 Power, Reset, and Clock Management.pdf

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