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Chapter 03 Power, Reset, and Clock Management.pdf

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Public Version<br />

PRCM Functional Description www.ti.com<br />

• Scope<br />

• Occurrence<br />

• Source type<br />

3.5.1.2.1 Scope<br />

A reset signal can be categorized according to its scope (the area of the device affected by that reset):<br />

• Global reset: Affects the entire device; all modules are reset. Generally, occurs when the device<br />

powers up or an abnormal operation is detected (the eFuse bad device is detected, etc.).<br />

• Local reset: Affects one power or reset domain. Generally, when a power domain transitions from off<br />

mode to active mode, or when a software-reset control bit for a domain is set, only the group of<br />

modules within that domain is affected.<br />

3.5.1.2.2 Occurrence<br />

A reset signal can be categorized depending on when the reset occurs:<br />

• Cold reset: Occurs only on device power up or in certain emulation modes. The cold reset is a global<br />

reset that affects every module in the device. It usually corresponds to the initial power-on reset.<br />

• Warm reset: Occurs when the device is in normal operating state. The warm reset is also a global<br />

reset, but it does not affect all the modules in the device. Usually, the device does not require a<br />

complete reboot on a warm reset. Several reset sources, such as the global software reset <strong>and</strong> the<br />

watchdog reset, are warm resets.<br />

Modules that behave differently in cold reset <strong>and</strong> warm reset have two reset signals: RST <strong>and</strong><br />

PWRON_RST. These reset signals reconstruct warm reset <strong>and</strong> cold reset in modules that require them.<br />

For a global warm reset, the PRCM module performs the following sequence:<br />

1. Applies a warm reset on all the modules, including modules built with RFFs.<br />

2. Applies a warm reset on the external modem interface.<br />

3. Drives the sys_nreswarm reset output low <strong>and</strong> holds it for a specified length of time (programmed in<br />

the PRCM.PRM_RSTTIME[7:0] RSTTIME1 bit field).<br />

4. All ongoing transactions on the voltage control I 2 C interface (I2C4 module) are aborted, <strong>and</strong> the<br />

external power IC is expected to return to nominal voltage values on receiving a sys_nreswarm reset.<br />

5. All power domains that are in off power mode are switched to on power mode.<br />

A global warm reset does not apply to the following modules of the device:<br />

• SDRC<br />

• System control module (SCM) (I/O control)<br />

• Part of PRM <strong>and</strong> CM registers (see note below)<br />

• 32-kHz synchronization timer<br />

• DPLL3 (see Section 3.5.1.9.2)<br />

• Emulation modules<br />

• eFuse farm<br />

NOTE: For information about the PRCM registers affected by the global warm reset, see the<br />

register mapping summary tables in Section 3.7, PRCM Register Manual.<br />

3.5.1.2.3 Source Type<br />

A reset can be categorized depending on whether it is software-controlled or hardware-triggered:<br />

• Software reset: Triggered by setting a bit in a configuration register of the PRCM module<br />

• Hardware reset: Triggered by a signal from a hardware module inside or outside the PRCM module<br />

3.5.1.3 <strong>Reset</strong> Sources<br />

Figure 3-21 is an overview of the reset sources.<br />

250 <strong>Power</strong>, <strong>Reset</strong>, <strong>and</strong> <strong>Clock</strong> <strong>Management</strong> SPRUGN4L–May 2010–Revised June 2011<br />

Copyright © 2010–2011, Texas Instruments Incorporated

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