Chapter 03 Power, Reset, and Clock Management.pdf

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PRCM Functional Description www.ti.com
Name I/O (1)
Table 3-17. WKUP Power Domain Reset Signals
Source/Destination (2)
Reset Domain
WKUP_RST I PRM Resets the GPTIMER1, WDTIMER2, GPIO 1
WKUP_RSTPWRON I PRM Resets the wake-up control module
MPU_WD_RST O PRM Global warm reset for PRM. Generated by WDTIMER2.
(1)
I = Input; O = Output
(2)
Source for an input signal and destination for an output signal
The PRM logic is reset on any global cold reset. Because the PRM logic is not reset in this case, PRM
registers that are sensitive to a warm reset must also be reset synchronously with the system clock when
a global warm reset occurs.
3.5.1.5.10 PER Power Domain
The PER power domain has two reset input signals (see Table 3-18).
Table 3-18. PER Power Domain Reset Signal
Name I/O (1) Source Reset Domain
PER_RST I PRCM Resets the UART[3, 4],
McBSP[2,3,4],
GPTIMER[2,..,9], WDTIMER3
modules
PER_RST_RET I PRCM Resets the GPIO [2,..,6]
modules
(1) I = Input; O = Output
3.5.1.5.11 SmartReflex Power Domain
The SmartReflex power domain has one reset input signal (see Table 3-19).
Table 3-19. SmartReflex Power Domain Reset Signal
Name I/O (1) Source Reset Domain
SR_RST I PRCM Resets the SR1 and SR2 modules
(1) I = Input; O = Output
3.5.1.5.12 DPLL Power Domains
The DPLL power domains for DPLL1, DPLL2, DPLL3, DPLL4 and DPLL5 each have one reset input
signal.
Table 3-20. DPLL Power Domain Reset Signals
Name I/O (1) Source Reset Domain
DPLL1_RSTPWRON I PRCM Resets the DPLL1 module
DPLL2_RSTPWRON I PRCM Resets the DPLL2 module
DPLL3_RSTPWRON I PRCM Resets the DPLL3 module
DPLL4_RSTPWRON I PRCM Resets the DPLL4 module
DPLL5_RSTPWRON I PRCM Resets the DPLL5 module
(1) I = Input; O = Output
They are asserted for any type of global cold reset.
3.5.1.5.13 EFUSE Power Domain
The EFUSE power domain has one reset input signal (see Table 3-21).
256 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011
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