Chapter 03 Power, Reset, and Clock Management.pdf

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Global power on reset sys_nrespwron BAD_DEVICE_RST Global warm reset EFUSE_DOM_RST DPLL1_DOM_RST DPLL2_DOM_RST DPLL3_SW_RST DPLL3_DOM_RST DPLL4_DOM_RST DPLL5_DOM_RST SR_DOM_RST Public Version PRCM Functional Description www.ti.com Figure 3-27. Power Domain Reset Management: Part 3 WKUP domain reset manager PRM reset manager EFUSE domain reset manager DPLL1 domain reset manager DPLL2 domain reset manager DPLL3 domain reset manager DPLL4 domain reset manager DPLL5 domain reset manager SMARTREFLEX domain reset manager WKUP_RST WKUP_RSTPWRON PRM_RSTPWRON SYNCT_RST EFUSE_RSTPWRON DPLL1_RSTPWRON DPLL2_RSTPWRON DPLL3_RSTPWRON DPLL4_RSTPWRON DPLL5_RSTPWRON SR_RST 262 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-026
Public Version www.ti.com PRCM Functional Description 3.5.1.8 Reset Summary Table 3-23 and Table 3-24 summarize the sources of global and local resets and their actions on the reset signals. Table 3-23. Global Reset Summary (1) Domain Resets Reset Sources Power Domain Signal Cold Reset Warm Reset MPU MPU_RST NEON NEON_RST IVA2 IVA2_RST1 IVA2_RST2 IVA2_RST3 IVA2_RSTPWRON SGX SGX_RST CORE CORE_RST CORE_RSTPWRON CORE_RST_RET CORE_RSTPWRON_RET CM_RSTPWRON_RET USBTLL_RST WKUP WKUP_RST SYNCT_RST PER PER_RST PER_RST_RET DSS DSS_RST CAM CAM_RST USBHOST USBHOST_RST DPLL1 DPLL1_RSTPWRON DPLL2 DPLL2_RSTPWRON DPLL3 DPLL3_RSTPWRON DPLL4 DPLL4_RSTPWRON DPLL5 DPLL5_RSTPWRON SR SR_RST EFUSE EFUSE_RSTPWRON sys_nres DPLL3_ sys_nres MPU_WD_ GLOBAL_ VDD1_VM_ VDD2_VM_ pweron SW_RST warm_in RST SW_RST RST RST (1) The shaded blocks identify the power domain reset signals triggered as a result of the reset source signal (at the head of the column). SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated 263
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