Chapter 03 Power, Reset, and Clock Management.pdf

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Public Version PRCM Functional Description www.ti.com Table 3-23. Global Reset Summary (1) (continued) Domain Resets Reset Sources Power Domain Signal Cold Reset Warm Reset BANDGAP BANDGAP_RSTPWRON Device pad (output) sys_nreswarm_out sys_nres DPLL3_ sys_nres MPU_WD_ GLOBAL_ VDD1_VM_ VDD2_VM_ pweron SW_RST warm_in RST SW_RST RST RST Table 3-24. Local Reset Summary (1) Domain Resets Reset Sources Power Domain Signal Cold Reset Warm Reset MPU MPU_RST NEON NEON_RST IVA2 IVA2_RST1 IVA2_RST2 IVA2_RST3 IVA2_RSTPWRON SGX SGX_RST CORE CORE_RST CORE_RST_RET CORE_RSTPWRON_RET CM_RSTPWRON_RET USBTLL_RST WKUP WKUP_RST SYNCT_RST PER PER_RST PER_RST_RET DSS DSS_RST CAM CAM_RST USBHOST USBHOST_RST DPLL1 DPLL1_RSTPWRON DPLL2 DPLL2_RSTPWRON CORE_DOM_ PER_DOM_ DPLL3_ BAD_ IVA2_SW_ IVA2_SW_ IVA2_SW_ RET_RST RET_RST SW_RST DEVICE_ RST1 RST2 RST3 RESET (1) The shaded blocks identify the power domain reset signals triggered as a result of the reset source signal (at the head of the column). 264 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com PRCM Functional Description Table 3-24. Local Reset Summary (1) (continued) Domain Resets Reset Sources Power Domain Signal Cold Reset Warm Reset DPLL3 DPLL3_RSTPWRON DPLL4 DPLL4_RSTPWRON DPLL5 DPLL5_RSTPWRON SR SR_RST EFUSE EFUSE_RSTPWRON BANDGAP BANDGAP_RSTPWRON Device pad (output) sys_nreswarm_out CORE_DOM_ PER_DOM_ DPLL3_ BAD_ IVA2_SW_ IVA2_SW_ IVA2_SW_ RET_RST RET_RST SW_RST DEVICE_ RST1 RST2 RST3 RESET SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated 265
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CORE power domain CM 96M_FCLK L3_IC
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WKUP power domain PRM WKUP L4 inter
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sys_xtalout sys_xtalin sys_boot6 sy
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DPLL3_ALWON_FCLK DPLL4_ALWON_FCLK s
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CORE_CLK SYS_CLK Source selection/d
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CM_SYS_CLK CM_32K_CLK 120M_FCLK OSC
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DPLL4_ALWON_FCLK 120M_FCLK 48M_FCLK
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96M_ALWON_FCLK 48M_FCLK SYS_CLK 32K
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SYS_CLK L4_ICLK Public Version www.
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Device power consumption OFF Switch
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1 2 3 4 5 6 Functional Functional c
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SYS_CLK Device state sys_nvmode2 VD
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Enable module functional clock Modu
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Enable module interface clock Modul
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Device 2. Voltage 3. Command config
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Chapter 03 Power, Reset, and Clock Management.pdf

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