Chapter 03 Power, Reset, and Clock Management.pdf

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PRCM Functional Description www.ti.com
3.5.1.9.2 Global Warm Reset Sequence
This section describes the global reset sequence.
The assumptions are:
• vdds, vdds_mem, vdda_dpll_pll, vdda_dpll_per, vdda_wkup_bg_bb and vdda_sram power rails are
regulated at 1.8 V.
• The VDD2 voltage domain (vdd_core power rail) is regulated at 1.0 V.
• The VDD1 voltage domain (vdd_mpu_iva power rail) is regulated at 1.2 V.
• The VDD3, VDD4, and VDD5 voltage domains are regulated at 1.2 V.
• The system is running:
– Resets are released.
– CORE DPLL and processor DPLL are locked.
Figure 3-29 shows the global warm reset sequence.
268 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011
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