Chapter 03 Power, Reset, and Clock Management.pdf

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Device Power control logic Generic voltage domain Retention Generic power domain Memory L4 interconnect Power Ctrl Idle, wakeup control Reset Ctrl Clock Ctrl Domain voltage Public Version PRCM Overview www.ti.com Figure 3-11. PRCM Overview VDD1 VDD2 VDD3 VDD4 VDD5 WKUP power domain PRCM Configuration registers Power, reset manager (PRM) Clock manager (CM) CORE power domain LDO LDO ctrl sys_nreswarm sys_nrespwron sys_32k sys_xtalout sys_xtalin sys_altclk sys_boot6 sys_clkreq sys_clkout1 sys_clkout2 sys_nvmode1 i2c4_scl sys_nvmode2 i2c4_sda sys_xtalgnd sys_off_mode System control module vdd_mpu_iva vdd_core vdda_wkup_bg_bb vdda_sram 238 Power, Reset, and Clock Management SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated prcm-010
Public Version www.ti.com PRCM Overview 3.2.2 PRCM Features The PRCM module includes the following features: • Managing 18 independent power domains • Controlling two scalable and three memory-selectable voltage modes • Handling idle/wake-up procedures • Allowing software and partial hardware control • Monitoring and handling wake-up events • Controlling system clock/reset input sources • Managing and distributing clocks and resets with high granularity • Handling power-up sequences • Debug and emulation features • Controlling external supply voltage regulation through dedicated high-speed (HS) I 2 C interface • CM implementation of RFFs to support DPS SPRUGN4L–May 2010–Revised June 2011 Power, Reset, and Clock Management Copyright © 2010–2011, Texas Instruments Incorporated 239
Page 1 and 2: Public Version Chapter 3 SPRUGN4L-M
Page 3 and 4: Normalized frequency 1.5 1.0 0.5 0
Page 5 and 6: Public Version www.ti.com Introduct
Page 7 and 8: Ctrl CLK1 Subsystem A Subsystem B C
Page 9 and 10: Voltage control Subsystem A Voltage
Page 11 and 12: Interface clocks Clock generator Fu
Page 13 and 14: SmartReflex functional clock Interr
Page 15: Public Version www.ti.com PRCM Over
Page 19 and 20: PRCM PRM CM Public Version www.ti.c
Page 21 and 22: PRCM PRM PRCM PRM Public Version ww
Page 23 and 24: Device Power control logic Retentio
Page 25 and 26: Public Version www.ti.com PRCM Inte
Page 27 and 28: Generic power domain Reset domain 1
Page 29 and 30: Device Reset sources MPU watchdog (
Page 31 and 32: Device Reset destinations IVA2 WKUP
Page 33 and 34: Public Version www.ti.com PRCM Func
Page 35 and 36: PRCM PRM Device sys_nreswarm_out sy
Page 37 and 38: GLOBAL_SW_RST DPLL3_SW_RST VDD1_VM_
Page 39 and 40: Global power on reset CM reset CORE
Page 47 and 48: Signal color-coding PRCM input PRCM
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Public Version www.ti.com PRCM Func
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PRCM PRM CM Public Version www.ti.c
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MPU_CLK IVA2_CLK L4_ICLK L3_ICLK 96
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sys_clkout1 sys_clkreq sys_xtalout
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PRM_192M_ALWON_CLK Public Version C
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DPLL_FCLK DPLL_ALWON_FCLK PRCM DPLL
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WKUP power domain PRM DPLL3_ALWON_F
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DPLL_FCLK DPLL_ALWON_FCLK PRCM DPLL
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MPU power domain MPU subsystem WKUP
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L3_ICLK CORE power domain CM SGX_L3
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From system control module MCBSP_CL
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PRM Public Version www.ti.com PRCM
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CORE power domain CM 96M_FCLK L3_IC
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WKUP power domain PRM WKUP L4 inter
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sys_xtalout sys_xtalin sys_boot6 sy
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DPLL3_ALWON_FCLK DPLL4_ALWON_FCLK s
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CORE_CLK SYS_CLK Source selection/d
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CM_SYS_CLK CM_32K_CLK 120M_FCLK OSC
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DPLL4_ALWON_FCLK 120M_FCLK 48M_FCLK
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96M_ALWON_FCLK 48M_FCLK SYS_CLK 32K
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SYS_CLK L4_ICLK Public Version www.
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Device power consumption OFF Switch
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1 2 3 4 5 6 Functional Functional c
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SYS_CLK Device state sys_nvmode2 VD
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SR_ALWON_FCLK PRM VDD1 error VDD1 v
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SmartReflex module: error SmartRefl
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Public Version www.ti.com PRCM Basi
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Selected source clock CM_POLCTRL [0
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sys_32k SYS_CLK WKUP Event sys_clkr
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Enable module functional clock Modu
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Enable module interface clock Modul
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Device power on 5. Interrupt genera
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Device 2. Voltage 3. Command config
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Frequency scaling when target OPP f
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Public Version www.ti.com PRCM Regi
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Chapter 03 Power, Reset, and Clock Management.pdf

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