Single-Chip Low Power RF Transceiver for Narrowband Systems ...

Transmitter side:
DCLK
DIO
“RF”
Receiver side:
“RF”
DCLK
DIO
CC1021
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
Data p rovided by UART (TX D)
FSK modulating signal,
internal in CC 102 1
Demodulated signal (NRZ),
intern al in CC1021
DCLK is use d as data output
provided by CC10 21.
Connect to UART (RXD)
DIO is not u sed in receive mo de. U sed only
as data inpu t in tra nsmit mode
Figure 11. Transparent Asynchronous
UART mode
(SEP_DI_DO = 1)
Tx
data
10. Dat a Rate Programming The da ta rate (baud rate) is programmable and depend s on the crystal frequency and
the progra mming of the CLOCK
(CLOCK_A and CLOCK_B) registers. The baud rate (B.R) is given by
f xosc
B.
R.
=
8 ⋅ (REF
_ DIV + 1)
⋅ DIV1⋅
DIV 2
where D IV1 and DIV2 are given by the
value of MCL K_DIV1 and
MCLK_DIV2.
Table 17 belo w shows some possible data
rates as a function
of crystal frequency in
synchronous mode. In asynchronous
transparent
UART mode any data rate up
to 153.6 kBaud can be used.
1 0 1 1 0 0 0 1 1 0 1
Figure 12. Manchester encoding
Data rate Crystal frequency [MHz]
Time
MCLK_DIV2[1: 0] DIV2
00 1
01 2
10 4
11 8
Table 15. DIV2 for different settings of
MCLK_DIV2
MCLK_DIV1[2:0] DIV1
000 2.5
001 3
010 4
011 7.5
100 12.5
101 40
110 48
111 64
Table 16. DIV1 for different settings of
MCLK_DIV1
SWRS045B Page 27 of 89