Single-Chip Low Power RF Transceiver for Narrowband Systems ...
Single-Chip Low Power RF Transceiver for Narrowband Systems ...
Single-Chip Low Power RF Transceiver for Narrowband Systems ...
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CC1021<br />
MAIN Register (00h)<br />
REGISTER NAME Default<br />
value<br />
Active Description<br />
MAIN[7] RXTX - - RX/TX switch,<br />
0: RX , 1: TX<br />
MAIN[6] F_REG - - Selection of Frequency Register,<br />
0: Register<br />
A, 1: Register B<br />
MAIN[5:4] PD_MODE[1:0] - - <strong>Power</strong> down<br />
mode<br />
0 (00): Receive Chain in power-down in TX, PA in power-down<br />
in<br />
RX<br />
1 (01): Receive Chain and PA in power-down in both TX and RX<br />
2 (10): Individual modules can be put in power-down by<br />
programming the POWERDOWN<br />
register<br />
3 (11): Automatic power-up sequencing<br />
is activated (see below)<br />
MAIN[3] FS_PD - H <strong>Power</strong> Down of Frequency Synthesizer<br />
MAIN[2] XOSC_PD - H <strong>Power</strong> Down of Crystal Oscillator Core<br />
MAIN[1] BIAS_PD - H <strong>Power</strong> Down of BIAS (Global Current<br />
Generator) and Crystal<br />
Oscillator Buffer<br />
MAIN[0] R ESET_N - L Reset, active low. Writing RESET_N low<br />
will write default values to<br />
all other registers than MAIN. Bits in MAIN do not have a default<br />
value and will be written directly through the configuration<br />
interface. Must be set high<br />
to complete reset.<br />
MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11)<br />
REGISTER NAME Default<br />
value<br />
Active Description<br />
MAIN[7] RXTX - - Automatic power-up sequencing only works in RX (RXTX=0)<br />
MAIN[6] F_REG - - Selection of Frequency Register, 0: Register A, 1: Register B<br />
MAIN[5:4] PD_MODE[1:0] - H Set PD_MODE[1:0]=3 (11) to enable sequencing<br />
MAIN[3:2] SEQ_CAL[1:0] - Controls PLL calibration be<strong>for</strong>e re-entering power-down<br />
0: Never pe libration as part of sequence<br />
1: Al ys p<br />
2: P rm<br />
3: Per<strong>for</strong>m 56 th -<br />
r<strong>for</strong>m PLL ca<br />
wa er<strong>for</strong>m PLL calibration at end of sequence<br />
erfo PLL calibration at end of every 16 sequence<br />
th sequence<br />
PLL calibration at end of every 2<br />
MAIN[1] SEQ_PD - ↑ ↑1: Put the chip in power down and wait <strong>for</strong> start of new power-up<br />
sequence<br />
MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write<br />
default values to<br />
all other registers than MAIN. Bits in MAIN do not have a default<br />
value and w ill be written directly through the configuration<br />
interface. Must be set high to complete reset.<br />
SWRS045B Page 66 of 89
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