Single-Chip Low Power RF Transceiver for Narrowband Systems ...
Single-Chip Low Power RF Transceiver for Narrowband Systems ...
Single-Chip Low Power RF Transceiver for Narrowband Systems ...
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
CC1021<br />
Loop C6 C7 C8 R2 R3 PLL turn-on time<br />
Comment<br />
filter no. [nF] [pF] [pF] [kΩ] [kΩ] [us]<br />
1 56 2200 560 3.3 10 1400 Up to 9.6 kBaud data rate.<br />
±5 kHz settling accuracy<br />
2 15 560 150 5.6 18 1300 Up to 19.2 kBaud data rate.<br />
±10 kHz settling accuracy<br />
3 3.9 120 33 12 39 1080 Up to 38.4 kBaud data rate.<br />
±15 kHz settling accuracy<br />
4 1.0 27 3.3 27 82 950 Up to 76.8 kBaud data rate.<br />
±20 kHz settling accuracy<br />
5 0.2 1.5 - 47 150 700 Up to 153.6 kBaud data rate.<br />
±50 kHz settling accuracy<br />
Table 25. Typical PLL turn-on time to within<br />
specified<br />
accuracy <strong>for</strong> different loop filter<br />
bandwidths.<br />
15.4. PLL Lock Time versus Loop Filter Bandwidth<br />
If calibration has been per<strong>for</strong>med the PLL<br />
lock<br />
time is the time needed <strong>for</strong> the PLL to<br />
lock<br />
to the desired frequency when going<br />
from RX to TX mode or vice versa. The<br />
PLL lock time depends on the PLL loop<br />
filter bandwidth. Table 26 gives the PLL<br />
lock time <strong>for</strong> different PLL loop filter<br />
bandwidths.<br />
Loop C6 C7 C8 R2 R3 PLL lock time<br />
Comment<br />
filter [nF] [pF] [pF] [kΩ] [kΩ]<br />
[us]<br />
no.<br />
1 2 3<br />
1 56 2200 560 3.3 10 400 140 490 Up to 9.6 kBaud<br />
data rate.<br />
(50 kHz)<br />
±5 kHz settling accuracy<br />
2 15 560 150 5.6 18 140 70 230 Up to 19.2 kBaud<br />
data rate.<br />
(100 kHz)<br />
±10 kHz settling accuracy<br />
3 3.9 120 33 12 39 75 50 180 Up to 38.4 kBaud data rate.<br />
(150 kHz)<br />
±15 kHz settling accuracy<br />
4 1.0 27 3.3 27 82 30 15 55 Up to 76.8 kBaud data rate.<br />
(200 kHz)<br />
±20 kHz settling accuracy<br />
5 0.2 1.5 - 47 150 14 14 28 Up to 153.6 kBaud data rate.<br />
(500 kHz)<br />
±50 kHz settling accuracy<br />
Table 26. Typical PLL lock time t o within specified accuracy <strong>for</strong> different loop filter<br />
bandwidths. 1) 307.2 kHz step, 2) step as given in brackets, 3) 1 MHz step.<br />
16. VCO and LNA Current Control<br />
The VCO current is programmable and<br />
should be set according to operating<br />
frequency, RX/TX mode and output power.<br />
Recommended settings <strong>for</strong> the<br />
VCO_CURRENT bits in the VCO register<br />
are shown in the register overview and<br />
also given by Smart<strong>RF</strong> ® Studio. The VCO<br />
current <strong>for</strong> frequency FREQ_A and<br />
FREQ_B can be programmed<br />
independently.<br />
The bias currents <strong>for</strong> the LNA, mixer and<br />
the LO and PA buffers are also<br />
programmable. The FRONTEND and the<br />
BUFF_CURRENT registers control these<br />
currents.<br />
SWRS045B Page 53 of 89