Single-Chip Low Power RF Transceiver for Narrowband Systems ...

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Transmitter side: DCLK DIO “RF” Receiver side: “RF” DCLK DIO Transmitter side: DCLK DIO “RF” Receiver side: “RF” DCLK DIO Clock provided by CC1021 CC1021 Data provided by microcontroller FSK modulating signal (NRZ), internal in CC1021 Demodulated signal (NRZ), internal in CC1021 Clock provided by CC1021 Data provided by CC1021 Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0) Clock provided by CC1021 Data provided by microcontroller FSK modulating signal (Manchester encoded), internal in CC1021 Demodulated signal (Manchester encoded), internal in CC1021 Clock provided by CC1021 Data provided by CC1021 Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0) SWRS045B Page 26 of 89
Transmitter side: DCLK DIO “RF” Receiver side: “RF” DCLK DIO CC1021 DCLK is not used in transmit mode, and is used as data output in receive mode. It can be set to default high or low in transmit mode. Data p rovided by UART (TX D) FSK modulating signal, internal in CC 102 1 Demodulated signal (NRZ), intern al in CC1021 DCLK is use d as data output provided by CC10 21. Connect to UART (RXD) DIO is not u sed in receive mo de. U sed only as data inpu t in tra nsmit mode Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1) Tx data 10. Dat a Rate Programming The da ta rate (baud rate) is programmable and depend s on the crystal frequency and the progra mming of the CLOCK (CLOCK_A and CLOCK_B) registers. The baud rate (B.R) is given by f xosc B. R. = 8 ⋅ (REF _ DIV + 1) ⋅ DIV1⋅ DIV 2 where D IV1 and DIV2 are given by the value of MCL K_DIV1 and MCLK_DIV2. Table 17 belo w shows some possible data rates as a function of crystal frequency in synchronous mode. In asynchronous transparent UART mode any data rate up to 153.6 kBaud can be used. 1 0 1 1 0 0 0 1 1 0 1 Figure 12. Manchester encoding Data rate Crystal frequency [MHz] Time MCLK_DIV2[1: 0] DIV2 00 1 01 2 10 4 11 8 Table 15. DIV2 for different settings of MCLK_DIV2 MCLK_DIV1[2:0] DIV1 000 2.5 001 3 010 4 011 7.5 100 12.5 101 40 110 48 111 64 Table 16. DIV1 for different settings of MCLK_DIV1 SWRS045B Page 27 of 89
Page 1 and 2: CC1021 CC1021 Single Chip Low Power
Page 3 and 4: CC1021 13. Transmitter ............
Page 5 and 6: 2. Absolute Maximum Ratings CC1021
Page 7 and 8: Parameter Spurious emission, radiat
Page 9 and 10: Input IP3 Parameter 433 MHz 102.4 k
Page 11 and 12: 4.3. RSSI / Carrier Sense Section P
Page 13 and 14: 4.6. Frequency Synthesizer Section
Page 15 and 16: 4.8. Current Consumption Parameter
Page 17 and 18: 6. Circuit Description RF_IN LNA RF
Page 19 and 20: Microcontroller configuration inter
Page 21 and 22: 8. Configuration Overview CC1021 ca
Page 23 and 24: 9.1. 4-wire Serial Configuration In
Page 25: 9.2. Signal Interface The CC1021 ca
Page 29 and 30: f ref f xosc = REF _ DIV + 1 FSK fr
Page 31 and 32: The DEC_DIV[2:0] bits in the FILTER
Page 33 and 34: 12.5. RSSI CC1021 has a built-in RS
Page 35 and 36: 12.6. Image Rejection Calibration F
Page 37 and 38: Blocker rejection [dB] 65 60 55 50
Page 39 and 40: • Frequency register setting is s
Page 41 and 42: 12.11. Carrier Sense The carrier se
Page 43 and 44: offset. The new frequency must be c
Page 45 and 46: Current [mA] / Output power [dBm] C
Page 47 and 48: CC1021 CC1021 RF_OUT RF_IN C60 L1 A
Page 49 and 50: 868 MHz CC1021 Figure 28: Typical o
Page 51 and 52: 15.2. VCO and PLL Self-Calibration
Page 53 and 54: CC1021 Loop C6 C7 C8 R2 R3 PLL turn
Page 55 and 56: Rese tCC102 0 WakeupCC1020ToRx/ Wak
Page 57 and 58: the "carrier sense" level (programm
Page 59 and 60: Item CL= 12 pF CL= 16 pF CL= 22 pF
Page 61 and 62: LNA_EN and PA_EN are used to contro
Page 63 and 64: frequencies is done through the MAI
Page 65 and 66: 26.1. CC1021 Register Overview CC10
Page 67 and 68: CC1021 INTERFACE Register (01h) REG
Page 69 and 70: CC1021 CLOCK_A Register (07h) REGIS
Page 71 and 72: CC1021 MODEM Register (0Dh) REGISTE
Page 73 and 74: CC1021 VGA1 Register (11h) REGISTER
Page 75 and 76: CC1021 VGA3 Register (13h) REGISTER
Page 77 and 78:
CC1021 FRONTEND Register (16h) REGI
Page 79 and 80:
BUFF_CURRENT Register (19h) REGISTE
Page 81 and 82:
CC1021 TEST1 Register (21h, for tes
Page 83 and 84:
CC1021 AFC Register (43h, read only
Page 85 and 86:
27. Package Description (QFN 32) CC
Page 87 and 88:
27.2. Recommended PCB Footprint for
Page 89 and 90:
29. General Information CC1021 Docu
Page 91:
*All dimensions are nominal PACKAGE
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