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11.3. Simulation Model
Figure 11.6.: UML class diagram of the test environment model
CInitPSM
Simple state machine for initialising the PSM in order that the EVC binary can
be connected to the required D-Bus adaptors (see Section 8.5). Also, it creates
the proxy to the DMI for the CDMI machine.
The interface ISignals provides global signals between the state machine classes and is used in
their concrete models, which will be introduced in detail in a subsection each. The complete
simulation model can also be found in Section H.3.
11.3.1. CInitPSM – Initialisation Model
The model of the state machine for the PSM initialisation is quite simple and only consists of
sequence of states, which is shown in Figure 11.7. The state “Waiting_for_start_of_PSM”
creates all simulative adaptors for hardware interfaces and waits for user input because the
generated EVC executable binary has to be started manually to connect to those adaptors via
proxies.
Afterwards, “Initialising_DMI” creates a proxy to access the DMI in the PSM part of the
EVC binary. The Boolean bInitialised signal is set to true to inform the other state machines
that all preconditions for the simulation process have been met.
Currently, the RT-Tester does not support the usage of final state objects, which are part of
the UML standard for state machines [64]. Therefore, the empty and dead state “Final” is used
to model that after the initialisation nothing more is executed by the CInitPSM state machine.
Most states in all state machines generate an output by the printf() function, which can
be used to generate the simulation traces described in Section 11.1.
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