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Chapter 11. openETCS Simulation
11.3.3. CEVC – EVC and Virtual Track Model
In contrast to the two preceding models, the CEVC state machine defines the virtual track and
also checks for required conditions for the EVC to detect errors during the simulation execution.
This means for the model that not only values are set in the simulative PSM hardware devices,
but also the @rttAssert-statement is used to detect deviations of the EVC from the expected
behaviour. On the top level of this state machine, all states correspond to a certain ETCS
Figure 11.12.: UML state machine diagram of the EVC behaviour
Mode while the virtual track is modelled in most states as sub-state machines. The correctness
of the EVC behaviour is tested on the top level and as well in the decompositions. Obviously,
not all ETCS Modes and possible transitions of the openETCS case study model in Chapter 10
were used in the EVC simulation model. This was done to keep a model which complexity and
size is still well interpretable in this document. Furthermore, the simulation in the openETCS
case study should primary demonstrate the applicability of the approach of a completely
model-driven tool chain. A small simulation model does not oppose this conclusion because
it can be extended without modifications of any openETCS DSL instance, like meta model,
generator, and domain framework.
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