Medianet Reference Guide - Cisco

Chapter 2
Medianet Bandwidth and Scalability
TxRing
Table 2-1
CIR Guidelines (continued)
Policed Bc or interface buffer (Kbyte)
CIR (Mbit/sec)
Less than
But more than
15 12 20
12 11 25
11 10 30
10 8.8 40
6.50 3.0 100
3.0 0.0 N/A
Because shapers can send Bc bytes at the beginning of each Tc time interval, and because shapers feed
indirectly into the TxRing of the interface, it is possible to tune the TxRing to accommodate this traffic.
TxRing
The TxRing and RxRings are memory structures shared by the main processor and the interface
processor (see Figure 2-7). This memory is arranged as a first in, first out (FIFO) queue. The ring can be
thought of as a list of memory pointers. For each ring, there is a read pointer and a write pointer. The
main processor and interface process each manage the pair of pointers appropriate to their function. The
pointers move independently of one another. The difference between the write and read pointers gives
the depth of the queue. Each pointer links a particle of memory. Particles are an efficient means of
buffering packets of all different sizes within a pool of memory. A packet can be spread over multiple
particles depending on the size of the packet. The pointers of a single packet form a linked list.
Figure 2-7
TxRings and RxRings
CPU
(IOS)
Interface
Queue
Rx
Memory
Tx
Memory
MAC
PHY
4b/5b
Magnetics
Interface
Queue
Rx
Memory
Tx
Memory
MAC
PHY
4b/5b
Magnetics
228642
The rest of the discussion on Cisco IOS architecture is out of scope for this section, but some key points
should be mentioned. Because a shaper can deposit Bc bytes of traffic onto an interface at the beginning
of each Tc time period, the TxRing should be at least large enough to handle this traffic. The exact
number of particles required depends on the average size of the packets to be sent, and the average
number of particles that a packet may link across. It may not be possible to know these values in all cases.
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Medianet Reference Guide
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