SPRING - UCSC Extension Silicon Valley

Hardware Systems and VLSI Engineering Engineering and Technology
Certificate Program
VLSI Engineering
Certificate Contact
Engineering and Technology Department, (408) 861-3860,
or e-mail program@ucsc-extension.edu.
Program Overview
Design engineers have broad responsibility for hardware
specification, analysis, logic design, verification, simulation,
synthesis, testing and maintenance of integrated
circuit products. While some have advanced degrees in
computer science or electrical engineering, few have the
practical education required for design, development and
maintenance of complex VLSI devices to accommodate
cost control, schedule and customer requirements.
The VLSI Engineering certificate program meets
this need. Taught by working professionals, this program
provides you with the tools, techniques and overall
understanding of the VLSI design process needed in
the design of small- to large-scale hardware products.
You will acquire a comprehensive understanding of
the entire design process and how each phase supports
the development of a VLSI product. The program also
prepares you for design work on VLSI projects at systems
or semiconductor companies and provides you with
required knowledge in simulation, verification, synthesis
and testing using modern EDA tools.
Certificate Requirements
To obtain the Certificate in VLSI Engineering, you must
successfully complete a total of 14 units.
Recommended Course Sequence
It is recommended that you take at least one course from
the “Design Methodology” category. Other courses may
be taken based on your interests and professional level.
For Information on Certificate
Applications and Transferring Credit
from Other Schools, see page 4.
Only one course may be shared between two
Engineering and Technology certificate programs unless
otherwise noted.
Courses
ASIC Physical Design, Advanced
CMPE.X446.9 (3.0 quarter units)
This course covers the advanced topics of ASIC front-toback
design automation. It introduces backend design
and low power techniques in 65nm technologies and
beyond. Topics include floor-planning considerations,
physical design synthesis, timing closure after detail
route, RC extraction and static timing analysis, congestion
analysis, IR drop, signal integrity, power planning and
analysis. The instructor will share his extensive experience
in ASIC implementation over many generations and will
also provide 90nm and 45nm lab exercises for students
to practice techniques learned in class.
Prerequisite(s): Basic knowledge of the backend design
flow from netlist to GDSII. Knowledge and hands-on experience
with Linux/Unix will be required for lab exercises.
SHAHROKH SHAKOURI, M.S.
SANTA CLARA LAB WITH ONLINE MATERIALS
10 meetings: Tuesdays, 6:30–9:30 pm, April 10–June 12.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 0634.(016)
Coding Theory and Applications,
Introduction
For course description, see page 57.
Design Simulation with Verilog
and SystemVerilog
CMPE.X400.002 (3.0 quarter units)
This course covers basic Verilog language. It introduces
students to the digital simulation process with hands-on
exercises using the simulation tool in the lab. The instructor
discusses simulation techniques, such as coding style,
event ordering, delta cycle debugging, zero width glitch,
race conditions, time slices and conditional compilation,
among other topics. The course also addresses simulation
performance and code coverage. The second half of the
course introduces the SystemVerilog language including
syntax and semantics. Examples are given to show how
these tools help designers with code compaction and
system verifications.
VLSI ENGINEERING certificate
14-unit minimum Units Course F W Sp Su
Design Methodology
Developing the Nanometer ASIC: From Spec to Silicon..........1.5...........3497 n n
Designing Xilinx CPLDs and FPGAs, Introduction..................3.0...........6346 n n
Logic and Functional Design
Digital Logic Design Using Verilog.........................................3.0...........0764 n n
Logic Synthesis, Introduction.................................................3.0...........4377 n n
SystemC, Introduction............................................................1.5.........19957 n n
Practical Logic Design by Example.........................................3.0.........22607 n n
Practical DFT Concepts for ASICs: With Nanometer Test
Enhancements...................................................................3.0...........5373 n n
IO Concepts and Protocols: PCI Express, Ethernet, and
Fibre Channel.....................................................................3.0.........22177 n n
Coding Theory and Applications, Introduction.......................3.0.........23389 n n
SystemVerilog and Verification
Design Simulation with Verilog and SystemVerilog...............3.0...........6932 n n
SystemVerilog for ASIC & FPGA Design.................................3.0.........20095 n n
SystemVerilog Assertions for Design Verification...................3.0.........20062 n
SystemVerilog for Advanced Design Verification....................3.0.........18966 n n
Structured Verification Using UVM
(Universal Verification Methodology).................................1.5...........0027 n n
Physical Design and Timing Closure
Physical Design Flow from Netlist to GDS II..........................3.0...........4436 n n
ASIC Physical Design, Advanced............................................3.0...........0634 n n
Timing Closure in IC Design...................................................3.0...........4775 n n
Circuit Design
Low-Power Design of Nano-Scale Digital Circuits.................3.0.........21941 m m m m
Analog IC Design, Introduction..............................................3.0...........3799 n
Mixed-Signal IC Design..........................................................3.0...........1999 n n
PLL and Clock/Data Recovery Circuits....................................3.0...........2283 n n
Designing CMOS Radio Frequency Integrated Circuits (RFIC).... 3.0.........22866
n
Jitter Essentials......................................................................1.5.........21321 n n
Comprehensive Signal and Power Integrity for
High-Speed Digital Systems................................................3.0.........22874 n n
n held in classroom m offered online p both classroom and online sessions are available
Visit ucsc-extension.edu for the most current program schedule.
Prerequisite(s): Knowledge of basic logic design and
familiarity with a high-level programming language
(e.g., C) and use of a text editor in the Linux
environment.
BENJAMIN TING, B.S.E.E., M.S.E.E..
SANTA CLARA LAB
10 meetings: Tuesdays, 6:30–9:30 pm, April 3–June 5.
Fee: $910 ($91 discount for early enrollment).
To enroll, use Section Number 6932.(012)
ACCESS TO ONLINE MATERIALS
online materials indicates that classroom instruction
is supplemented with online materials or activities.
Students who enroll in these courses, and in those
which are entirely online, will receive logon information
within 24 hours. However, valid logon information
may not be active until the course’s start date.
54
Enroll on our Web site with a credit card. It’s the fastest, easiest way to get started. Visit ucsc-extension.edu.