SPRING - UCSC Extension Silicon Valley

Engineering and Technology Hardware Systems and VLSI Engineering
Designing CMOS Radio Frequency
Integrated Circuits (RFIC)
CMPE.X400.429 (3.0 quarter units)
This course addresses both the theoretical and practical
aspects of CMOS RFIC circuit design. The course begins
with a review of the CMOS transistor model and RLC
network. It introduces the concepts of impedance matching,
two-port noise, and linearity. The instructor provides
in-depth explanations of the design and analysis of lownoise
amplifiers, mixers, voltage-controlled oscillators,
synthesizers, and power amplifiers. To reinforce the skills
learned in this course, students will develop their own
designs for major wireless transceiver blocks. The course
also includes discussion of the design trade-offs in
various radio architectures.
Prerequisite(s): “Analog IC Design, Introduction.”
Familiar with circuit analysis and small-signal models.
Have prior experience with a circuit simulator.
MIN “ADAM” CHU, Ph.D.
SANTA CLARA LAB WITH ONLINE MATERIALS
8 meetings: Saturdays, 9 am–1 pm, April 21–June 16.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 22866.(004)
Designing Xilinx CPLDs and FPGAs,
Introduction
For course description, see page 52.
IO Concepts and Protocols:
PCI Express, Ethernet, and Fibre Channel
For course description, see page 53.
Low-Power Design of
Nano-Scale Digital Circuits
EE.X400.097 (3.0 quarter units)
This course introduces advanced topics in nano-scale
(below 90nm) VLSI device and circuit design. Highperformance
and low-power design issues in modern
and future nano-scale CMOS technologies are discussed
in detail. Students will learn low power design approaches
and techniques at different levels of abstraction. New
design techniques will be introduced to deal with nano
circuit designs under excessive leakage and process
variations. Several non-classical CMOS devices for circuit
design in such technologies will be explored. Prospects
of future non-silicon nanotechnologies will be reviewed.
Prerequisite(s): Knowledge of CMOS technology and
digital circuit design in CMOS is recommended, but
an overview will be provided.
HAMID MAHMOODI, Ph.D.
ONLINE, April 16–July 30.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 21941.(015)
PLL and Clock/Data Recovery Circuits
CMPE.X444.7 (3.0 quarter units)
Phase-locked-loop (PLL) circuits are used extensively
in system and chip designs for frequency multiplication,
data extraction, and re-timing purposes. This course
provides students with the knowledge required for
analysis and design of PLL circuits and their applications
in clock and data-recovery circuits. The instructor will
discuss various components involved in the design of a
PLL circuit. Topics include transceiver design, high-speed
I/O, ring and LC oscillators, charge-pump PLL, practical
issues at transistor-level design, noise and jitter in PLL,
delay-locked loop, frequency multiplier, and clock and
data recovery circuits.
Prerequisite(s): Basic knowledge of RLC circuits, MOS
transistors, simple analog circuits such as single stage
amplifiers, differential amplifiers, current sources and
concept of feedback, and simple digital circuits such
as logic gates, flip-flops, shift registers and counters.
KAMRAN IRAVANI, M.S.
SANTA CLARA CLASSROOM
11 meetings: Fridays, 6:30–9:30 pm, April 20–June 29.
Fee: $1020 ($102 discount for early enrollment).
To enroll, use Section Number 2283.(016)
Practical Logic Design By Example
CMPE.X400.425 (3.0 quarter units)
This course teaches the logic design of real-world
digital systems. The emphasis is on how to break down
a complex digital design specification, logic design of the
sub-designs, and integration into the top level design,
validated with respect to the specification. The course
goes deep into the logic design of common to re-useable
sub-systems. There will be a guided project to design a
complete digital system from specification to validation.
Students will also learn the concepts of designing for
speed, power, area, testability, cost, and physical design.
Prerequisite(s): “Design Simulation with Verilog and
SystemVerilog.” Experience with some EDA tools (such
as synthesis and STA) and Linux/Unix computing is
required for the lab exercises. Familiarity with Verilog
language is required. Students are expected to have
completed a college level course in logic.
YACOUB EL-ZIQ, Ph.D.
SANTA CLARA LAB
10 meetings: Mondays, 6:30–9:30 pm, April 9–June 18.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 22607.(006)
Structured Verification Using UVM
(Universal Verification Methodology)
CMPE.X439.8 (1.5 quarter units)
This five week course covers structured verification
development using the Universal Verification Methodology
(UVM) environment. It begins with an overview of
UVM’s basic building blocks, followed by an examination
of the components and transactions they use to communicate.
Test and component creation and sequence
generation will be discussed and reviewed. Students
learn the effectiveness of modular and encapsulated,
ready-to-use and configurable verification environments.
Concepts introduced in class are reinforced in the lab
with a real-world design project.
Prerequisite(s): “SystemVerilog for Advanced Design
Verification” course or equivalent experience.
NICK ARREGUY, B.S.E.E..
SANTA CLARA LAB
5 meetings: Mondays, 6:30–9:30 pm, May 7–June 11.
Fee: $660 ($66 discount for early enrollment).
To enroll, use Section Number 0027.(021)
Free Program Overview
Open House Event for
Embedded Systems, VLSI,
and Network Engineering
For event description, see page 50.
SANTA CLARA CLASSROOM
Tuesday, 6:30–8:30 pm, March 27.
No fee, but registration required.
To enroll, use Section Number 22403.(006)
SANTA CLARA CLASSROOM
Tuesday, 6:30–8:30 pm, May 29.
No fee, but registration required.
To enroll, use Section Number 22403.(007)
LOGIC AND FUNCTIONAL DESIGN
COURSES
In addition to teaching languages and tools, we
also offer courses in logic and functional design of
hardware. This knowledge is applicable in the chip,
board, and system industries.
• Digital Logic Design using Verilog
• Practical Logic Design by Example
• Practical DFT Concepts for ASICs:
With Nanometer Test Enhancements
• Introduction to SystemC
• IO Concepts and Protocols: PCI Express,
Ethernet, and Fibre Channel
Course Readers, Textbooks
and Other Instructional Resources
Students are responsible for obtaining the required
instructional materials for all courses. A variety of
media are used. Please review the section details
at the bottom of the course description pages on
our Web site.
Instructors may specify any of the following:
• Printed course readers from our on-demand service
provider, Content Management Corporation (CMC)
• Electronic course materials from our online
learning platform, UCSC Extension Online
• Textbooks (required and recommended). See pages
5 and 94 and visit ucsc-extension.edu/bookstore.
• Other materials distributed via e-mail either by the
Academic Department or the instructor
Students should acquire or access their materials
prior to the first class meeting. For full instructions,
go to ucsc-extension.edu/course-materials.
Copyright © 2012 The Regents of the University of California. All Rights Reserved. 55