SPRING - UCSC Extension Silicon Valley

Hardware Systems and VLSI Engineering / Network Engineering and Systems Security Engineering and Technology
3NEW
SystemC, Introduction
CMPE.X400.334 (1.5 quarter units)
SystemC is gaining popularity among system design,
semiconductor, and IP companies. This course will help
you build a solid understanding of all major aspects
of SystemC, with a focus on modeling and system
verification. The course begins with an overview of
the Open SystemC Initiative (OSCI) and the C++ class
library. Language syntax and modules are covered.
In the hands-on lab, you will learn the key event
management methods, including timing specification,
concurrency, interfaces, channels and ports. The course
also covers debugging, and includes an overview of the
SystemC Verification Library (SCV) and Transaction Level
Modeling (TLM).
Prerequisite(s): Experience with C++ language is
required. Knowledge of Verilog, SystemVerilog, VHDL or
logic simulation (such as VCS) is strongly recommended
but not required.
YASSER KHAN, B.S.
SANTA CLARA LAB WITH ONLINE MATERIALS
5 meetings: Thursdays, 6:30–9:30 pm, April 26–May 24.
Fee: $660 ($66 discount for early enrollment).
To enroll, use Section Number 19957.(004)
SystemVerilog for ASIC and FPGA Design
CMPE.X400.363 (3.0 quarter units)
This course prepares hardware engineers, ASIC and
FPGA designers, and design-support staff to use the
high-level syntax of SystemVerilog to design, debug, and
synthesize digital logic for ASICs, FPGAs, and IP cores.
Students will learn SystemVerilog’s basic building blocks
and language constructs, including synthesizable data
types and operators, structures and unions, 2-D arrays
and loops, and the bus interface unit. In lab sessions,
students will write code and synthesize it into digital
logic and bus fabric, using both ASIC and FPGA tools.
Prerequisite(s): “Logic Synthesis, Introduction” or
“Designing Xilinx CPLDs and FPGAs, Introduction.”
Familiarity with either Verilog or VHDL. No prior
exposure to SystemVerilog is needed.
CHARLES DANCAK, M.S.E.E.
SANTA CLARA LAB WITH ONLINE MATERIALS
10 meetings: Wednesdays, 6:30–9:30 pm,
April 11–June 13.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 20095.(008)
ACCESS TO ONLINE MATERIALS
online materials indicates that classroom instruction
is supplemented with online materials or activities.
Students who enroll in these courses, and in those
which are entirely online, will receive logon information
within 24 hours. However, valid logon information
may not be active until the course’s start date.
SystemVerilog Assertions
for Design Verification
CMPE.X400.348 (3.0 quarter units)
This course introduces SystemVerilog Assertion (SVA)
concepts and syntax, using both small examples and
a realistic design. It covers a range of topics, from the
basics of the SVA constructs to using the OVL checker
library. It also covers methods for capturing design
intent based on design specification into assertions.
Writing and debugging assertions in the design using
advanced SVA constructs is also covered. Students learn
to write assertions for functional coverage and formal
or semi-formal verification. This is a lab-based course
with hands-on exercises using assertions, dynamic
simulations and formal or semi-formal verification.
Prerequisite(s): Knowledge of basic logic design and
familarity with a hardware description language.
HAIHUI CHEN, M.S.E.E.
SANTA CLARA LAB WITH ONLINE MATERIALS
10 meetings: Thursdays, 6:30–9:30 pm, April 5–June 7.
Fee: $1020 ($102 discount for early enrollment).
To enroll, use Section Number 20062.(006)
Timing Closure in IC Design
CMPE.X455.3 (3.0 quarter units)
This course begins with basic timing concepts and STA
methodology. You will learn what needs to be timed and
how to setup a run for STA. The course exposes students
to constraints, exceptions and “what if” analysis. It also
explains how to address timing violations in ECO mode.
Nanotechnology topics including noise analysis, prevention
and on-chip variations are covered. The instructor
shares practical experiences meeting timing closure,
budgeting and debugging. This is a lab course using
Primetime tools and test cases for hands-on practical
experience.
Prerequisite(s): “Developing the Nanometer ASIC: From
Spec to Silicon.” Linux/Unix skills are required for lab
exercises.
ARVIND VIDYARTHI, M.S.
SANTA CLARA LAB WITH ONLINE MATERIALS
10 meetings: Wednesdays, 6:30–9:30 pm,
April 18–June 20.
Fee: $980 ($98 discount for early enrollment).
To enroll, use Section Number 4775.(028)
Also of Interest
Embedded Systems Hardware
Architectures, Introduction
For course description, see page 53.
Perl Programming I
For course description, see page 64.
Perl Programming II
For course description, see page 64.
Network Engineering
and Systems Security
The Network Engineering and Systems Security Program
combines two previous certificate programs: Network
Engineering and Management, and Systems and
Network Security. Courses you have previously taken
in either program can all apply toward the certificate.
The certificate program includes tracks with network
and security focuses beyond the fundamental courses.
Certificate Program
Network Engineering
and Systems Security
Certificate Contact
Engineering and Technology Department, (408) 861-3860,
or e-mail program@ucsc-extension.edu.
Program Overview
Computer networks are the global platform on which
companies conduct business and people communicate.
As a result, virtually every industry needs engineering
and IT professionals who can design, manage and support
networks which deliver competitive advantage and
have high security. This certificate program addresses
that need with a curriculum that begins with network
fundamentals, and then moves on to advanced study
in specialized areas of networking and system security.
The curriculum is designed to reflect the industry’s
latest developments and practices. You will acquire
career-oriented skills and practical knowledge, and
many courses include hands-on learning in our labs.
Certificate Requirements
To obtain the Certificate in Network Engineering
and Systems Security, you must complete 14 units,
representing 140 hours of instruction. For additional
requirements, see page 4.
Recommended Course Sequence
We recommend that you begin with the fundamental
courses. Students are expected to satisfy the prerequisites
for each course before enrolling in more advanced courses.
For Information on Certificate
Applications and Transferring Credit
from Other Schools, see page 4.
Only one course may be shared between two
Engineering and Technology certificate programs unless
otherwise noted.
Courses
Cloud Computing, Introduction
For course description, see page 65.
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Enroll on our Web site with a credit card. It’s the fastest, easiest way to get started. Visit ucsc-extension.edu.