Buffer Insertion Basics - Computer Engineering & Systems Group ...

and the results are reported in [6]. One metric that reveals the scaling is critical buffer length
- the minimum distance beyond which inserting an optimally placed and sized buffer makes the
interconnect delay less than that of the corresponding unbuffered wire. When wire delay increases
due to the technology scaling, the critical buffer length becomes shorter, i.e., the distance that a
buffer can comfortably drive shrinks. According to [6], the buffer critical length decreases by
68% when the VLSI technology migrates from 90nm to 45nm (for two generations). Please note
that the critical buffer length scaling significantly outpaces the VLSI technology scaling which is
roughly 0.5× for every two generations. If we look at the percentage of block level nets requiring
buffers, it grows from 5.8% in 90nm technology to 19.6% in 45nm technology [6]. Perhaps the
most alarming result is the scaling of buffer count [6] which predicts that 35% of cells will be
buffers in 45nm technology as opposed to only 6% in 90nm technology.
The dramatic buffer scaling undoubtedly generates large and profound impact to VLSI circuit
design. With millions of buffers required per chip, almost nobody can afford to neglect the importance
of buffer insertion as compared to a decade ago when only a few thousands of buffers
are needed for a chip [7]. Due to this importance, buffer insertion algorithms and methodologies
need to be deeply studied on various aspects. First, a buffer insertion algorithm should deliver
solutions of high quality since interconnect and circuit performance largely depend on the way
that buffers are placed. Second, a buffer insertion algorithm needs to be sufficiently fast so that
millions of nets can be optimized in reasonable time. Third, accurate delay models are necessary to
ensure that buffer insertion solutions are reliable. Fourth, buffer insertion techniques are expected
to simultaneously handle multiple objectives, such as timing, power and signal integrity, and their
tradeoffs. Last but not the least, buffer insertion should interact with other layout steps, such as
placement and routing, as the sheer number of buffers has already altered the landscape of circuit
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