Buffer Insertion Basics - Computer Engineering & Systems Group ...

[30] F. J. Liu, J. Lillis, and C. K. Cheng. Design and implementation of a global router based on a
new layout-driven timing model with three poles. In Proceedings of the IEEE International
Symposium on Circuits and Systems, pages 1548–51, 1997.
[31] J. Qian, S. Pullela, and L. T. Pillage. Modeling the effective capacitance for the RC interconnect
of CMOS gates. IEEE Transactions on Computer-Aided Design, 13(12):1526–1535,
December 1994.
[32] S. R. Nassif and Z. Li. A more effective C eff . In Proceedings of the IEEE International
Symposium on Quality Electronic Design, pages 648–653, 2005.
[33] B. Tutuianu, F. Dartu, and L. Pileggi. Explicit RC-circuit delay approximation based on
the first three moments of the impulse response. In Proceedings of the ACM/IEEE Design
Automation Conference, pages 611–616, 1996.
[34] C. J. Alpert, F. Liu, C. V. Kashyap, and A. Devgan. Closed-form delay and slew metrics made
easy. IEEE Transactions on Computer-Aided Design, 23(12):1661–1669, December 2004.
[35] C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion with accurate gate and interconnect
delay computation. In Proceedings of the ACM/IEEE Design Automation Conference, pages
479–484, 1999.
[36] C.-K. Cheng, J. Lillis, S. Lin, and N. Chang. Interconnect analysis and synthesis. Wiley
Interscience, New York, NY, 2000.
[37] S. Hassoun, C. J. Alpert, and M. Thiagarajan. Optimal buffered routing path constructions for
single and multiple clock domain systems. In Proceedings of the IEEE/ACM International
Conference on Computer-Aided Design, pages 247–253, 2002.
42