Buffer Insertion Basics - Computer Engineering & Systems Group ...

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with minimum C. In van Ginneken’s algorithm, it takes O(bn) to find one best candidate at each buffer position. According to convex pruning, it is easy to see that all best candidates are on the convex hull. The following lemma says that if we sort candidates in increasing Q and C order from left to right, then as we add wires to the candidates, we always move to the left to find the best candidates. Lemma 1 For any T(v), let nonredundant candidates after convex pruning be α 1 ,α 2 ,...,α k , in increasing Q and C order. Now add wire e to each candidate α j and denote it as α j + e. For any buffer type B i , if α j gives the maximum P i (α j ) and α k gives the maximum P i (α k +e), then k ≤ j. The following lemma says the best candidate can be found by local search, if all candidates are convex. Lemma 2 For any T(v), let nonredundant candidates after convex pruning be α 1 ,α 2 ,...,α k , in increasing Q and C order. If P i (α j−1 ) ≤ P i (α j ), P i (α j ) ≥ P i (α j+1 ), then α j is the best candidate for buffer type B i and P i (α 1 ) ≤ · · · ≤ P i (α j−1 ) ≤ P i (α j ), P i (α j ) ≥ P i (α j+1 ) ≥ · · · ≥ P i (α k ). With the above two lemmas and convex pruning, best candidates are founded in amortized O(n) time in [40] and O(b) time in [41] 1 , which are more efficient than van Ginneken’s algorithm. 1 In [40], Lemma 1 is presented differently. It says if all buffers are sorted decreasingly according to driving resistance, then the best candidates for each buffer type in such order is from left to right. 36
5.5 Implicit Representation Van Ginnken’s algorithm uses explicit representation to store slack and capacitance values, and therefore it takes O(bn) time when adding a wire. It is possible to use implicit representation to avoid explicit updating of candidates. In the implicit representation, C(v,α) and Q(v,α) are not explicitly stored for each candidate. Instead, each candidate contains 5 fields: q, c, qa, ca and ra 2 . When qa, ca and ra are all 0, q and c give Q(v,α) and C(v,α), respectively. When a wire is added, only qa, ca and ra in the root of the tree ( [39]) or as global variables themselves ( [41]) are updated. Intuitively, qa represents extra wire delay, ca represents extra wire capacitance and ra represents extra wire resistance. It takes only O(1) time to add a wire with the implicit representation [39, 41]. For example, in [41], when we reach an edge e with resistance R(e) and C(e), qa, ra and ca are updated to reflect new values of Q and C of all previous candidates in O(1) time, without actually touching any candidate: qa = qa + R(e) · C(e)/2 + R(e) · ca, ca = ca + C(e), ra = ra + R(e). 2 In [41], only 2 fields, q and c, are necessary for each candidate. qa, ca and ra are global variables for each 2-pin segment. 37
Page 1 and 2: Chapter 26 Buffer Insertion Basics
Page 3 and 4: layout design. Many of these issues
Page 5 and 6: The length of each segment can be o
Page 7 and 8: assigned to a buffer position is al
Page 9 and 10: 3.2.2 Buffer insertion Suppose that
Page 11 and 12: 3.5 Example Algorithm: van Ginneken
Page 13 and 14: and those dictated by solutions in
Page 15 and 16: the algorithm maintains two solutio
Page 17 and 18: given slew constraint, it is pruned
Page 19 and 20: the tolerable noise margin (NM) of
Page 21 and 22: where R e is the wire resistance. T
Page 23 and 24: 4.7 Higher Order Delay Modeling Man
Page 25 and 26: admittance Y u (s) after merging th
Page 27 and 28: and m (0) AB = m(0) AD = 1. Now the
Page 29 and 30: In GiLa, the λ u for a leaf node u
Page 31 and 32: Algorithm: GiLa(T u )/GiLa(T u,v )
Page 33 and 34: v R min v 2 v 3 ... v k v 1 T(v 1 )
Page 35: list, we only need to check its nei
Page 39 and 40: [6] P. Saxena, N. Menezes, P. Cocch
Page 41 and 42: [22] J. Cong and K.-S. Leung. Optim
Page 43: [38] P. Cocchini. A methodology for

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