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The actual value of Q and C of each candidate α, are decided as follows Q(α) = q − qa − ra · c, C(α) = c + ca. (27) Implicit representation is applied on balance tree in [39], where the operation of adding a wire takes O(b log n) time. It is applied on a sorted linked list in [41], where the operation of adding a wire takes O(1) time. References [1] J. Cong. An interconnect-centric design flow for nanometer technologies. Proceedings of IEEE, 89(4):505–528, April 2001. [2] J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl. Interconnect limits on gigascale integration (GSI) in the 21st century. Proceedings of IEEE, 89(3):305–324, March 2001. [3] R. Ho, K. W. Mai, and M. A. Horowitz. The future of wires. Proceedings of IEEE, 89(4):490– 504, April 2001. [4] A. B. Kahng and G. Robins. On optimal interconnections for VLSI. Kluwer Academic Publishers, Boston, MA, 1995. [5] J. Cong, L. He, C.-K. Koh, and P. H. Madden. Performance optimization of VLSI interconnect layout. Integration: the VLSI Journal, 21:1–94, 1996. 38
[6] P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick. Repeater scaling and its impact on CAD. IEEE Transactions on Computer-Aided Design, 23(4):451–463, April 2004. [7] J. Cong. Challenges and opportunities for design innovations in nanometer technologies. SRC Design Sciences Concept Paper, 1997. [8] M. S. Bazaraa, H. D. Sherali, and C. M. Shetty. Nonlinear programming: theory and algorithms. John Wiley and Sons, 1993. [9] C. J. Alpert and A. Devgan. Wire segmenting for improved buffer insertion. In Proceedings of the ACM/IEEE Design Automation Conference, pages 588–593, 1997. [10] C. C. N. Chu and D. F. Wong. Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ACM Transactions on Design Automation of Electronic Systems, 6(3):343– 371, July 2001. [11] L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 865–868, 1990. [12] J. Lillis, C. K. Cheng, and T. Y. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE Journal of Solid-State Circuits, 31(3):437–447, March 1996. [13] N. Menezes and C.-P. Chen. Spec-based repeater insertion and wire sizing for on-chip interconnect. In Proceedings of the International Conference on VLSI Design, pages 476–483, 1999. 39
Page 1 and 2: Chapter 26 Buffer Insertion Basics
Page 3 and 4: layout design. Many of these issues
Page 5 and 6: The length of each segment can be o
Page 7 and 8: assigned to a buffer position is al
Page 9 and 10: 3.2.2 Buffer insertion Suppose that
Page 11 and 12: 3.5 Example Algorithm: van Ginneken
Page 13 and 14: and those dictated by solutions in
Page 15 and 16: the algorithm maintains two solutio
Page 17 and 18: given slew constraint, it is pruned
Page 19 and 20: the tolerable noise margin (NM) of
Page 21 and 22: where R e is the wire resistance. T
Page 23 and 24: 4.7 Higher Order Delay Modeling Man
Page 25 and 26: admittance Y u (s) after merging th
Page 27 and 28: and m (0) AB = m(0) AD = 1. Now the
Page 29 and 30: In GiLa, the λ u for a leaf node u
Page 31 and 32: Algorithm: GiLa(T u )/GiLa(T u,v )
Page 33 and 34: v R min v 2 v 3 ... v k v 1 T(v 1 )
Page 35 and 36: list, we only need to check its nei
Page 37: 5.5 Implicit Representation Van Gin
Page 41 and 42: [22] J. Cong and K.-S. Leung. Optim
Page 43: [38] P. Cocchini. A methodology for

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