Buffer Insertion Basics - Computer Engineering & Systems Group ...

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[30] F. J. Liu, J. Lillis, and C. K. Cheng. Design and implementation of a global router based on a new layout-driven timing model with three poles. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1548–51, 1997. [31] J. Qian, S. Pullela, and L. T. Pillage. Modeling the effective capacitance for the RC interconnect of CMOS gates. IEEE Transactions on Computer-Aided Design, 13(12):1526–1535, December 1994. [32] S. R. Nassif and Z. Li. A more effective C eff . In Proceedings of the IEEE International Symposium on Quality Electronic Design, pages 648–653, 2005. [33] B. Tutuianu, F. Dartu, and L. Pileggi. Explicit RC-circuit delay approximation based on the first three moments of the impulse response. In Proceedings of the ACM/IEEE Design Automation Conference, pages 611–616, 1996. [34] C. J. Alpert, F. Liu, C. V. Kashyap, and A. Devgan. Closed-form delay and slew metrics made easy. IEEE Transactions on Computer-Aided Design, 23(12):1661–1669, December 2004. [35] C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion with accurate gate and interconnect delay computation. In Proceedings of the ACM/IEEE Design Automation Conference, pages 479–484, 1999. [36] C.-K. Cheng, J. Lillis, S. Lin, and N. Chang. Interconnect analysis and synthesis. Wiley Interscience, New York, NY, 2000. [37] S. Hassoun, C. J. Alpert, and M. Thiagarajan. Optimal buffered routing path constructions for single and multiple clock domain systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 247–253, 2002. 42
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Page 1 and 2: Chapter 26 Buffer Insertion Basics
Page 3 and 4: layout design. Many of these issues
Page 5 and 6: The length of each segment can be o
Page 7 and 8: assigned to a buffer position is al
Page 9 and 10: 3.2.2 Buffer insertion Suppose that
Page 11 and 12: 3.5 Example Algorithm: van Ginneken
Page 13 and 14: and those dictated by solutions in
Page 15 and 16: the algorithm maintains two solutio
Page 17 and 18: given slew constraint, it is pruned
Page 19 and 20: the tolerable noise margin (NM) of
Page 21 and 22: where R e is the wire resistance. T
Page 23 and 24: 4.7 Higher Order Delay Modeling Man
Page 25 and 26: admittance Y u (s) after merging th
Page 27 and 28: and m (0) AB = m(0) AD = 1. Now the
Page 29 and 30: In GiLa, the λ u for a leaf node u
Page 31 and 32: Algorithm: GiLa(T u )/GiLa(T u,v )
Page 33 and 34: v R min v 2 v 3 ... v k v 1 T(v 1 )
Page 35 and 36: list, we only need to check its nei
Page 37 and 38: 5.5 Implicit Representation Van Gin
Page 39 and 40: [6] P. Saxena, N. Menezes, P. Cocch
Page 41: [22] J. Cong and K.-S. Leung. Optim

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