Buffer Insertion Basics - Computer Engineering & Systems Group ...

and m (0)
AB = m(0) AD
= 1. Now the moments from A to C can be computed via moment multiplication
as follows.
m (i)
AC = i∑
(m (j)
AB · m(i−j)
j=0
BC ) (24)
One property of Elmore delay that makes it attractive for timing optimization is that the delays
are additive. This property does not hold for higher order delay models. Consequently, a
non-critical sink in a subtree may become a critical sink depending the value of upstream resistance
[35]. Therefore, one must store the moments for all the paths to downstream sinks during the
bottom-up candidate solution propagation.
4.7.3 Accurate gate delay
A popular gate delay model with decent accuracy consists of the following three steps:
1. Compute a π−model of the driving point admittance for the RC interconnect using the techniques
introduced in Section 4.7.1.
2. Given the π−model and the characteristics of the driver, compute an effective capacitance
C eff [31, 32].
3. Based on C eff , compute the gate delay using k−factor equations or lookup table [36].
4.8 Flip-flop Insertion
The technology scaling leads to decreasing clock period, increasing wire delay and growing chip
size. Consequently, it often takes multiple clock cycles for signals to reach their destinations along
global wires. Traditional interconnect optimization techniques such as buffer insertion are inade-
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