Buffer Insertion Basics - Computer Engineering & Systems Group ...

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can be determined by l e,max = − R b R − I T(v) + I √ ( R b R )2 + ( I T(v) ) I 2 + 2NS(v) I · R (18) Depending on the timing criticality of the net, the noise-aware buffer insertion problem can be formulated in two different ways: (A) minimize total buffer cost subject to noise constraints; (B) maximize timing slack subject to noise constraints. The algorithm for (A) is a bottom-up dynamic programming procedure which inserts buffers greedily as far apart as possible [27]. Each partial solution at node v is characterized by a 3-tuple of downstream noise current I T(v) , noise slack NS(v) and buffer assignment M. In the solution propagation, the noise current is accumulated in the same way as the downstream capacitance in van Ginneken’s algorithm. Likewise, noise slack is treated like the timing slack (or required arrival time). This algorithm can return an optimal solution for a multi-sink tree T = (V,E) in O(|V | 2 ) time. The core algorithm of noise constrained timing slack maximization is similar as van Ginneken’s algorithm except that the noise constraint is considered. Each candidate solution at node v is represented by a 5-tuple of downstream capacitance C v , required arrival time q(v), downstream noise current I T(v) , noise slack NS(v) and buffer assignment M. In addition to pruning inferior solutions according to the (C,q) pair, the algorithm eliminates candidate solutions that violate the noise constraint. At the source, the buffering solution not only has optimized timing performance but also satisfies the noise constraint. 22
4.7 Higher Order Delay Modeling Many buffer insertion methods [11, 12, 28] are based on the Elmore wire delay model [29] and a linear gate delay model for the sake of simplicity. However, the Elmore delay model often overestimates interconnect delay. It is observed in [30] that Elmore delay sometimes has over 100% overestimation error when compared to SPICE. A critical reason of the overestimation is due to the neglection of the resistive shielding effect. In the example of Figure 8, the Elmore delay from node A to B is equal to R 1 (C 1 + C 2 ) assuming that R 1 can see the entire capacitance of C 2 despite the fact that C 2 is somewhat shielded by R 2 . Consider an extreme scenario where R 2 = ∞ or there is open circuit between node B and C. Obviously, the delay from A to B should be R 1 C 1 instead of the Elmore delay R 1 (C 1 + C 2 ). The linear gate delay model is inaccurate due to its neglection of nonlinear behavior of gate delay in addition to resistive shielding effect. In other words, a gate delay is not a strictly linear function of load capacitance. A R 1 R 2 C 2 C 1 B C Figure 8: Example of resistive shielding effect. The simple and relatively inaccurate delay models are suitable only for early design stages such as buffer planning. In post-placement stages, more accurate models are needed because (1) optimal buffering solutions based on simple models may be inferior since actual delay is not being optimized; (2) simplified delay modeling can cause a poor evaluation of the trade-off between total buffer cost and timing improvement. In more accurate delay models, the resistive shielding effect is considered by replacing lumped load capacitance with higher order load admittance estimation. 23
Page 1 and 2: Chapter 26 Buffer Insertion Basics
Page 3 and 4: layout design. Many of these issues
Page 5 and 6: The length of each segment can be o
Page 7 and 8: assigned to a buffer position is al
Page 9 and 10: 3.2.2 Buffer insertion Suppose that
Page 11 and 12: 3.5 Example Algorithm: van Ginneken
Page 13 and 14: and those dictated by solutions in
Page 15 and 16: the algorithm maintains two solutio
Page 17 and 18: given slew constraint, it is pruned
Page 19 and 20: the tolerable noise margin (NM) of
Page 21: where R e is the wire resistance. T
Page 25 and 26: admittance Y u (s) after merging th
Page 27 and 28: and m (0) AB = m(0) AD = 1. Now the
Page 29 and 30: In GiLa, the λ u for a leaf node u
Page 31 and 32: Algorithm: GiLa(T u )/GiLa(T u,v )
Page 33 and 34: v R min v 2 v 3 ... v k v 1 T(v 1 )
Page 35 and 36: list, we only need to check its nei
Page 37 and 38: 5.5 Implicit Representation Van Gin
Page 39 and 40: [6] P. Saxena, N. Menezes, P. Cocch
Page 41 and 42: [22] J. Cong and K.-S. Leung. Optim
Page 43: [38] P. Cocchini. A methodology for

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