Buffer Insertion Basics - Computer Engineering & Systems Group ...

4.7 Higher Order Delay Modeling
Many buffer insertion methods [11, 12, 28] are based on the Elmore wire delay model [29] and
a linear gate delay model for the sake of simplicity. However, the Elmore delay model often
overestimates interconnect delay. It is observed in [30] that Elmore delay sometimes has over
100% overestimation error when compared to SPICE. A critical reason of the overestimation is
due to the neglection of the resistive shielding effect. In the example of Figure 8, the Elmore delay
from node A to B is equal to R 1 (C 1 + C 2 ) assuming that R 1 can see the entire capacitance of C 2
despite the fact that C 2 is somewhat shielded by R 2 . Consider an extreme scenario where R 2 = ∞
or there is open circuit between node B and C. Obviously, the delay from A to B should be R 1 C 1
instead of the Elmore delay R 1 (C 1 + C 2 ). The linear gate delay model is inaccurate due to its
neglection of nonlinear behavior of gate delay in addition to resistive shielding effect. In other
words, a gate delay is not a strictly linear function of load capacitance.
A
R 1 R 2
C 2
C 1
B C
Figure 8: Example of resistive shielding effect.
The simple and relatively inaccurate delay models are suitable only for early design stages
such as buffer planning. In post-placement stages, more accurate models are needed because (1)
optimal buffering solutions based on simple models may be inferior since actual delay is not being
optimized; (2) simplified delay modeling can cause a poor evaluation of the trade-off between total
buffer cost and timing improvement. In more accurate delay models, the resistive shielding effect
is considered by replacing lumped load capacitance with higher order load admittance estimation.
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