Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

OCP-IP Confidential
3.1 Debug interface definitions
The programming of registers that contain either configuration or status information in the
debug IP blocks may be JTAG-mapped or Memory-mapped. Either or both modes of control
and access are acceptable, based on specific system requirements.
In the Memory-mapped case the master port of the main debug core provides the programming
of the debug block registers that have an address in the main memory space. The master OCP
data port is not part of the OCP debug port. This allows one core to be the main debug agent.
The debugger sends instructions over JTAG to this core and the core accomplishes all actions
through the main system bus. Then this one core needs special priority access to unlock stuck
interfaces and locked transactions. Signals for this purpose like “Abort” and “Force” are part of
the debug control interface.
In the more general and system independent JTAG-mapped register variant the JTAG is part of
the OCP Debug Interface. Debugger sends instructions to the cores over JTAG and the debug
registers are part of a JTAG-TAP controller. Optional “Abort” and “Force” signals are also
JTAG controlled. (Time stamp in 4.6 and trace compression A.2 is explained later.)
For simplicity, debug ports discussed are limited to 1149.1 JTAG interfaces, as defined in OCP
2.0 specification (and many other documents). This restriction is initially done to simplify the
interfaces initially addressed. The intent is not that implementation be necessarily limited to
1149.1 JTAG. With a separate interface layer debug interfaces discussed can be compatible
with Nexus TAP and protocol and other debug interfaces – CJTAG, SerDes (Aurora),
single/dual wire, etc, which are not discussed in this release of this document.
Debug Blocks with both JTAG and Memory Mapped interface
CHIP INTERCONNECT NETWORK
Extra Trace Bus
Nexus
S
M DEBUG S M DEBUG S M DEBUG S M DEBUG
DEBUG
S
CORE
DEBUG
Compress
TRIGGER
CORE
DEBUG
STAMP
Compress
counter
TRIGGER
1/3 system clock
BUS
OBSERVER
DEBUG
STAMP
Compress
counter
TRIGGER
Hyper Debug
DEBUGCntrl
TRACE
CNTRL
Voltage
Island
STAMP
counter
Separate
Clock
Domain
CORE
DEBUG
STAMP
Compress
counter
TRIGGER
JTAG
PORT
TRACE BUFFER Ch1,2
JTAG DFT
TRACE
PORT
Nexus
Dual Channel Synchronous Debug with Debug IP-Blocks
Figure 3.2 –Multi core Synchronous Debug Implementation
3.2 Basic Socket Level Debug interfaces
Processor run control interfaces are typically implemented via the JTAG interface and by
debug mode signals in the IP. The use of JTAG debug interfaces is supported via the OCP2.0
specification and is it is assumed that any JTAG signals are decoded at the core level JTAG
TAP (Test Access Point) and are not addressed in this document. A JTAG only debug interface
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